Method of fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-2017170185-A1
Application number	US-201615262025-A
Country	US
Kind code	A1
Filing date	Sep 12, 2016
Priority date	Dec 10, 2015
Publication date	Jun 15, 2017
Grant date	—

Abstract

A method of fabricating a semiconductor device includes forming a mold structure including a lower support layer and an upper support layer sequentially stacked on a substrate, doping portions of the upper and lower support layers with impurities to divide each of the upper and lower support layers into first portions doped with the impurities and a second portion surrounding the first portions in a plan view, and removing the first portions of the upper and lower support layers to form an upper support pattern having first openings and a lower support pattern having second openings.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, the method comprising:
forming a mold structure including a lower support layer and an upper support layer that are sequentially stacked on a substrate; doping portions of the upper and lower support layers with impurities to divide each of the upper and lower support layers into first portions doped with the impurities and a second portion surrounding the first portions in a plan view; and removing the first portions of the upper and lower support layers to form an upper support pattern having first openings and a lower support pattern having second openings.

2 . The method as claimed in claim 1 , wherein the first portions are doped with the impurities by an ion implantation process.

3 . The method as claimed in claim 1 , wherein the impurities include at least one of boron (B), carbon (C), germanium (Ge), or fluorine (F).

4 . The method as claimed in claim 1 , wherein:
the first portions include at least one of SiBN, SiCN, SiGeN, or SiFN, and the second portion includes silicon nitride.

5 . The method as claimed in claim 1 , wherein:
forming of mold structure includes sequentially stacking a lower mold layer, the lower support layer, an upper mold layer, and the upper support layer on the substrate, and the lower and upper mold layers include a material having an etch selectivity with respect to the second portions of the upper and lower support layers.

6 . The method as claimed in claim 1 , further comprising:
forming lower electrodes before doping the portions of the upper and lower support layers, the lower electrodes penetrating the mold structure and being spaced apart from each other on the substrate.

7 . The method as claimed in claim 6 , wherein:
a portion of a sidewall of an upper portion of each of the lower electrodes is in contact with the upper support pattern, and a portion of a sidewall of a lower portion of each of the lower electrodes is in contact with the lower support pattern.

8 . A method of fabricating a semiconductor device, the method comprising:
forming a mold structure including a mold layer and a preliminary support layer that are sequentially stacked on a substrate; forming lower electrodes penetrating the mold structure; doping portions of the preliminary support layer with impurities to form a support layer including first portions doped with the impurities, the first portions being in contact with portions of the lower electrodes; removing the first portions of the support layer to form a support pattern having openings exposing portions of the lower electrodes and the mold layer; and removing the mold layer exposed through the openings to expose sidewalls of the lower electrodes.

9 . The method as claimed in claim 8 , wherein:
the mold structure further includes an upper mold layer and a preliminary upper support layer sequentially stacked on the preliminary support layer, and the method further includes, after forming the lower electrodes, patterning the preliminary upper support layer to form an upper support pattern having upper openings exposing portions of the lower electrodes and portions of the upper mold layer.

10 . The method as claimed in claim 9 , wherein the openings overlap with the upper openings when viewed in a plan view.

11 . The method as claimed in claim 9 , wherein an upper portion of the upper support pattern is doped with the impurities during the formation of the support layer.

12 . The method as claimed in claim 11 , wherein the upper portion of the upper support pattern is removed when the first portions of the support layer are removed, such that a thickness of the upper support pattern is reduced.

13 . The method as claimed in claim 11 , wherein the upper portion of the upper support pattern includes a same material as the first portions of the support layer.

14 . The method as claimed in claim 8 , wherein:
the mold structure further includes an upper mold layer and a preliminary upper support layer sequentially stacked on the preliminary support layer, doping the portions of the preliminary support layer with impurities to form the support layer further includes doping portions of the preliminary upper support layer with the impurities to form an upper support layer including second portions doped with the impurities, and the second portions overlap with the first portions when viewed in a plan view.

15 . The method as claimed in claim 14 , further comprising, before forming the support pattern:
removing the second portions of the upper support layer using an etching solution to form an upper support pattern having upper openings exposing portions of the lower electrodes and portions of the upper mold layer.

16 . A method of fabricating a semiconductor device, the method comprising:
forming a mold structure including at least a first mold layer, a lower support layer, a second mold layer and an upper support layer that are sequentially stacked on a substrate; forming lower electrodes to extend through the upper support layer, second mold layer, lower support layer and first mold layer, each lower electrode contacting a contact plug in the substrate; forming a mask pattern on the mold structure to define regions in the mold structure for forming upper electrodes; doping the upper support layer and the lower support layer in the regions for forming upper electrodes with impurities such that each of the upper and lower support layers are divided into first portions doped with the impurities, the first portions being in the regions for forming the upper electrodes, and a second portion surrounding the first portions in a plan view, such that the first portions of the upper and lower support layers have an etching selectivity with respect to the second portions; and removing the first portion of the upper support layer, the second mold layer, the first portion of the lower support layer and the first mold layer in the region for forming upper electrodes, wherein portions of the lower electrodes adjoining the region for forming upper electrodes are exposed, and wherein at least one of the first portion of the upper support layer, the second mold layer, the first portion of the lower support layer and the first mold layer in the region for forming upper electrodes is removed by wet etching using an etchant having an etch selectivity that preferentially removes the first portions relative to the second portions.

17 . The method as claimed in claim 16 , wherein:
the lower support layer and the upper support layer include silicon nitride, and the impurities include at least one of boron (B), carbon (C), germanium (Ge), or fluorine (F), such that at least one of SiBN, SiCN, SiGeN, or SiFN is formed in the first portions of the lower support layer and the upper support layer.

18 . The method as claimed in claim 16 , further including forming a dielectric layer on the exposed portions of the lower electrodes and forming the upper electrodes on the dielectric layer.

19 . The method as claimed in claim 16 , wherein:
second portions of the lower support layer remaining after removing the doped lower support layer form a lower support pattern, a portion of a sidewall of a lower portion of each of the lower electrodes being in contact with the lower support pattern, and removing the first mold layer exposes a bottom surface of the first support pattern.

20 . The method as claimed in claim 19 , wherein,
second portions o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Eun
• Kim Yong Kwan
• Ahn Sehyoung
• Jang Semyeong
• Choi Jaehyoung
• Kim Bong-Soo
• Hwang Yoosang

Classifications

• H10P30/40

  into insulating materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L27/1085 Primary

  Electricity · mapped topic

• H01L21/283

  Electricity · mapped topic

• H01L21/31155

  Electricity · mapped topic