Semiconductor memory device including vertical barrier

Patent metadata

Field	Value
Publication number	US-11056503-B2
Application number	US-201916580817-A
Country	US
Kind code	B2
Filing date	Sep 24, 2019
Priority date	Feb 25, 2019
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A semiconductor memory device includes a dummy stack structure having a first stack structure and a second stack structure formed on the first stack structure. The semiconductor memory device also includes a cell stack structure surrounding the dummy stack structure. The semiconductor memory device further includes a vertical barrier disposed at a boundary between the cell stack structure and the dummy stack structure, the vertical barrier including a first part formed on a sidewall of the first stack structure and a second part formed on a sidewall of the second stack structure. A sectional area of the first part of the vertical barrier is greater than a sectional area of the second part of the vertical barrier at a height at which a boundary between the first stack structure and the second stack structure is disposed.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a dummy stack structure including a first stack structure and a second stack structure formed on the first stack structure;
a cell stack structure surrounding the dummy stack structure;
a vertical barrier disposed at a boundary between the cell stack structure and the dummy stack structure, the vertical barrier including a first part formed on a sidewall of the first stack structure and a second part formed on a sidewall of the second stack structure; and
a source structure disposed under the vertical barrier, and surrounding a protrusion part of a lower part of the vertical barrier,
wherein a sectional area of the first part of the vertical barrier is greater than a sectional area of the second part of the vertical barrier at a height at which a boundary between the first stack structure and the second stack structure is disposed, and
wherein the source structure includes:
a source layer overlapped by the cell stack structure; and
a dummy source stack structure overlapped by the dummy stack structure.

2. The semiconductor memory device of claim 1 , wherein the vertical barrier comprises:
a dummy-side dielectric layer extending to surround a sidewall of the dummy stack structure;
a semiconductor pattern extending to surround the dummy-side dielectric layer; and
a cell-side dielectric layer extending to surround the semiconductor pattern, wherein the cell-side dielectric layer is on an opposite side of the semiconductor pattern from the dummy-side dielectric layer.

3. The semiconductor memory device of claim 2 , wherein the vertical barrier further includes a core insulating layer surrounded by the semiconductor pattern.

4. The semiconductor memory device of claim 2 , wherein each of the dummy-side dielectric layer and the cell-side dielectric layer includes a tunnel insulating layer, a data storage layer, and a blocking insulating layer, which are sequentially stacked on a surface of the semiconductor pattern.

5. The semiconductor memory device of claim 2 , wherein:
the semiconductor pattern includes a protrusion part that protrudes farther toward a bottom of the vertical barrier than the cell stack structure and the dummy stack structure, and
the protrusion part of the semiconductor pattern is surrounded by the source structure.

6. The semiconductor memory device of claim 5 , further comprising:
a lower insulating layer penetrating the source structure, the lower insulating layer overlapped by the dummy stack structure; and
a contact plug extending to penetrate the dummy stack structure and the lower insulating layer.

7. The semiconductor memory device of claim 6 , wherein the dummy-side dielectric layer is disposed between the source structure and the protrusion part of the semiconductor pattern, and is spaced apart from the cell-side dielectric layer.

8. The semiconductor memory device of claim 7 , wherein:
the source layer is overlapped by the cell stack structure, the source layer being in contact with the protrusion part of the semiconductor pattern between the dummy-side dielectric layer and the cell-side dielectric layer; and
the dummy source stack structure is disposed between the lower insulating layer and the dummy-side dielectric layer at the same height as the source layer.

9. The semiconductor memory device of claim 1 , further comprising:
a channel structure penetrating the cell stack structure; and
a memory layer disposed between the cell stack structure and the channel structure.

10. The semiconductor memory device of claim 1 , wherein the cell stack structure includes interlayer insulating layers and conductive patterns, which are alternately stacked,
wherein each of the first stack structure and the second stack structure of the dummy stack structure includes dummy interlayer insulating layers and sacrificial insulating layers, which are alternately stacked.

11. A semiconductor memory device comprising:
a source structure;
a first source contact structure and a second source contact structure, each extending from the source structure;
a dummy stack structure disposed between the first source contact structure and the second source contact structure;
a cell stack structure surrounding the dummy stack structure between the first source contact structure and the second source contact structure, the cell stack structure overlapping the source structure;
a semiconductor pattern extending along a boundary between the dummy stack structure and the cell stack structure, the semiconductor pattern extending to the inside of the source structure; and
dielectric layers extending along an outer wall of the semiconductor pattern, the dielectric layers separated from each other by the source structure,
wherein the source structure extends to be in contact with sidewalls of the semiconductor pattern, which face the first source contact structure and the second source contact structure.

12. The semiconductor memory device of claim 11 , wherein the dielectric layers include:
a dummy-side dielectric layer disposed between the dummy stack structure and the semiconductor pattern; and
a cell-side dielectric layer disposed between the cell stack structure and the semiconductor pattern.

13. The semiconductor memory device of claim 12 , wherein the dummy-side dielectric layer is disposed between the source structure and the semiconductor pattern.

14. The semiconductor memory device of claim 11 , further comprising:
a lower insulating layer penetrating the source structure;
a peripheral circuit structure overlapped by the source structure and the lower insulating layer; and
a contact plug penetrating the dummy stack structure and the lower insulating layer, the contact plug connected to the peripheral circuit structure.

15. The semiconductor memory device of claim 11 , wherein the dummy stack structure includes dummy interlayer insulating layers and sacrificial insulating layers, which are alternately stacked, and
the cell stack structure includes interlayer insulating layers and conductive patterns, which are alternately stacked.

16. The semiconductor memory device of claim 11 , wherein each of the dielectric layers includes a tunnel insulating layer, a data storage layer, and a blocking insulating layer, which are sequentially stacked on a surface of the semiconductor pattern.

17. The semiconductor memory device of claim 11 , wherein the source structure includes:
a first source layer extending to be overlapped by the dummy stack structure and the cell stack structure;
a dummy source stack structure disposed between the dummy stack structure and the first source layer, the dummy source stack structure spaced apart from the semiconductor pattern; and
a second source layer disposed between the first source layer and the cell stack structure, the second source layer being in direct contact with the semiconductor pattern.

18. The semiconductor memory device of claim 17 , wherein the dummy source stack structure includes at least one protective layer and at least one sacrificial source layer, which are stacked between the first source layer and the dummy stack structure.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic