Sealed interface power module housing

US2023053718A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023053718-A1
Application numberUS-202117405653-A
CountryUS
Kind codeA1
Filing dateAug 18, 2021
Priority dateAug 18, 2021
Publication dateFeb 23, 2023
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A number of different sealed interfaces for power modules are described. In one example, a sealed interface includes a printed circuit board including a contact pad for power conduction to a bus bar of the printed circuit board, a semiconductor module including at least one power transistor, a terminal pin electrically coupled to the power module, and a housing for the power module. The housing includes an open terminal aperture that extends through the housing. The printed circuit board is seated upon the open terminal aperture, to close and seal the open terminal aperture, with the contact pad positioned within the open terminal aperture. The terminal pin contacts the contact pad of the printed circuit board within the open terminal aperture, and the open terminal aperture comprises a transitional feature to abate electric field intensity around an interface between the open terminal aperture and the printed circuit board.

First claim

Opening claim text (preview).

Therefore, the following is claimed: 1 . A sealed interface for a power module, comprising: a printed circuit board comprising a contact pad for power conduction to a bus bar of the printed circuit board; a semiconductor module comprising at least one power transistor; a terminal pin electrically coupled to the power module; and a housing for the power module, the housing comprising an open terminal aperture that extends through the housing, wherein: the printed circuit board is seated upon the open terminal aperture, to close and seal the open terminal aperture, with the contact pad positioned within the open terminal aperture; the terminal pin contacts the contact pad of the printed circuit board within the open terminal aperture; and the open terminal aperture comprises a transitional feature to abate electric field intensity around an interface between the open terminal aperture and the printed circuit board. 2 . The sealed interface for the power module according to claim 1 , wherein the terminal pin comprises a spring for contact compression with the contact pad of the printed circuit board. 3 . The sealed interface for the power module according to claim 1 , further comprising: a plurality of terminal pins electrically coupled to the power module, wherein: the housing comprises a plurality of open terminal apertures that extend through the housing, with at least one of the plurality of terminal pins extending within each of the plurality of open terminal apertures. 4 . The sealed interface for the power module according to claim 3 , wherein: a voltage potential between two open terminal apertures among the plurality of open terminal apertures is at least 10,000 V; and a center-to-center spacing between two open terminal apertures among the plurality of open terminal apertures is about 6 mm. 5 . The sealed interface for the power module according to claim 1 , wherein: the open terminal aperture comprises a planar rim surface; and the planar rim surface is elevated from an exterior surface of the housing. 6 . The sealed interface for the power module according to claim 5 , wherein a planar surface of the printed circuit board is secured over and contacts the planar rim surface. 7 . The sealed interface for the power module according to claim 5 , wherein the transitional feature comprises at least one of a curved surface or an angled surface with respect to the planar rim surface. 8 . The sealed interface for the power module according to claim 1 , wherein the open terminal aperture comprises a planar rim surface, an inner wall surface, and an outer wall surface. 9 . The sealed interface for the power module according to claim 8 , wherein the inner wall surface comprises the transitional feature between an interior surface of the housing and the planar rim surface. 10 . The sealed interface for the power module according to claim 8 , wherein the outer wall surface comprises the transitional feature between an exterior surface of the housing and the planar rim surface. 11 . The sealed interface for the power module according to claim 8 , wherein: the inner wall surface comprises a first transitional feature between an interior surface of the housing and the planar rim surface; and the outer wall surface comprises a second transitional feature between an exterior surface of the housing and the planar rim surface. 12 . The sealed interface for the power module according to claim 11 , wherein: the first transitional feature comprises an angled surface with respect to the planar rim surface; and the second transitional feature comprises a curved surface with respect to the planar rim surface. 13 . The sealed interface for the power module according to claim 1 , wherein the printed circuit board comprises at least one internal metal layer electrically coupled with the contact pad and extending within the printed circuit board to dislocate electric field intensity away from the interface between the open terminal aperture and the printed circuit board. 14 . A power module, comprising: a semiconductor module comprising at least one power transistor; a terminal pin electrically coupled to the power module; and a housing for the power module, the housing comprising an open terminal aperture that extends through the housing, wherein: the terminal pin extends within the open terminal aperture; and the open terminal aperture comprises a transitional feature to abate electric field intensity around the open terminal aperture. 15 . The power module according to claim 14 , further comprising: a plurality of terminal pins electrically coupled to the power module, wherein: the housing comprises a plurality of open terminal apertures that extend through the housing, with at least one of the plurality of terminal pins extending within each of the plurality of open terminal apertures. 16 . The power module according to claim 14 , wherein: the open terminal aperture comprises a planar rim surface; and the planar rim surface is elevated from an exterior surface of the housing. 17 . The power module according to claim 14 , wherein the transitional feature comprises at least one of a curved surface or an angled surface with respect to the planar rim surface. 18 . The power module according to claim 14 , wherein the open terminal aperture comprises a planar rim surface, an inner wall surface, and an outer wall surface. 19 . The power module according to claim 18 , wherein the inner wall surface comprises the transitional feature between an interior surface of the housing and the planar rim surface. 20 . The power module according to claim 18 , wherein the outer wall surface comprises the transitional feature between an exterior surface of the housing and the planar rim surface.

Assignees

Inventors

Classifications

  • for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • Solid or gel fillings · CPC title

  • Containers comprising an insulating or insulated base · CPC title

  • H10W76/12Primary

    characterised by their shape · CPC title

Patent family

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Frequently asked questions

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What does patent US2023053718A1 cover?
A number of different sealed interfaces for power modules are described. In one example, a sealed interface includes a printed circuit board including a contact pad for power conduction to a bus bar of the printed circuit board, a semiconductor module including at least one power transistor, a terminal pin electrically coupled to the power module, and a housing for the power module. The housing…
Who is the assignee on this patent?
Virginia Tech Intellectual Properties Inc, Univ Nottingham
What technology area does this patent fall under?
Primary CPC classification H10W76/12. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Feb 23 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).