Memory device having 2-transistor vertical memory cell

Patent metadata

Field	Value
Publication number	US-2023030364-A1
Application number	US-202217961282-A
Country	US
Kind code	A1
Filing date	Oct 6, 2022
Priority date	Dec 26, 2018
Publication date	Feb 2, 2023
Grant date	—

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.

First claim

What is claimed is:

1 . An apparatus comprising:
a memory cell including:
a first transistor including a charge storage structure and a first channel region separated from the charge storage structure; and
a second transistor including a second channel region coupled to the charge storage structure;
a conductive region coupled to a first portion of the first channel region; a first data line coupled to a second portion of the first channel region; a second data line coupled to the second channel region, the second channel region being between the charge storage structure and the second data line, each of the first and second data lines including a length in a first direction; and at least one access line including length in a second direction and separated from the first channel region and the second channel region.

2 . The apparatus of claim 1 , wherein the at least one access line includes:
a first access line located on a first level of the apparatus and separated from the first channel region by a first dielectric material; and a second access line located on a second level of the apparatus and separated from the second channel region by a second dielectric material, and wherein the first data line is located on a third level of the apparatus, the first level being between the second and third levels.

3 . The apparatus of claim 1 , further comprising:
an additional memory cell, the additional memory cell including:
a first additional transistor including an additional charge storage structure, and a first additional channel region coupled to the conductive region and separated from the additional charge storage structure; and
a second additional transistor including a second additional channel region coupled to the additional charge storage structure;
a third data line coupled to the first additional channel region; and a fourth data line coupled to the second additional channel region, the second additional channel region being between the additional charge storage structure and the fourth data line, the third and fourth data lines including a length in the first direction, wherein the at least one access line includes a portion spanning across part of the first channel region and part of the first additional channel region.

4 . The apparatus of claim 3 , wherein the at least one access line includes:
a first access line located on a first level of the apparatus and separated from the first channel region by a first dielectric material; and a second access line located on a second level of the apparatus and separated from the second channel region by a second dielectric material, wherein: the first access line includes the portion spanning across part of the first channel region and part of the first additional channel region; and the second access line includes a portion spanning across part of the second channel region and part of the second additional channel region.

5 . The apparatus of claim 1 , further comprising a trench including a bottom, wherein the charge storage structure is formed in a first location of the trench, the second channel region is formed in a second location of the trench, and the charge storage structure is between the bottom of the trench and the second channel region.

6 . The apparatus of claim 1 , wherein the charge storage material and the second channel region include different materials.

7 . An apparatus comprising:
a memory cell including:
a first transistor including a charge storage structure and a first channel region separated from the charge storage structure; and
a second transistor including a second channel region coupled to the charge storage structure;
a conductive region coupled to a first portion of the first channel region;
a first data line coupled to a second portion of the first channel region; and
a second data line coupled to the second channel region, the second channel region located over the charge storage structure and the second channel region being between the charge storage structure and the second data line.

8 . The apparatus of claim 7 , wherein the first and second transistors have different threshold voltages.

9 . The apparatus of claim 7 , wherein the first channel region includes:
a first portion located on a first side of the charge storage structure; a second portion located on a second side of the charge storage structure; and a third portion located between the charge storage structure and the substrate.

10 . The apparatus of claim 7 , wherein the first and second channel regions include different materials.

11 . The apparatus of claim 7 , wherein the charge storage structure includes a semiconductor material.

12 . The apparatus of claim 7 , wherein the charge storage structure includes metal.

13 . The apparatus of claim 7 , further comprising an access line shared by the first and second transistor.

14 . The apparatus of claim 7 , further comprising:
a first access line coupled to the first transistor; and a second access line coupled to the second transistor.

15 . The apparatus of claim 7 , wherein the first channel region is to conduct current between the first and second portions of the first channel region during an operation performed on the memory cell.

16 . An apparatus comprising:
a memory cell including:
a first transistor including a charge storage structure and a first channel region separated from the charge storage structure; and
a second transistor including a second channel region coupled to the charge storage structure;
a first data line having a length in a first direction and coupled to the first channel region; a second data line having a length in the first direction and coupled to the second channel region; a conductive region coupled to the first channel region; and at least one access line associated with at least one of the first and second transistors, the least one access line having a length in a second direction and located below the second data line.

17 . The apparatus of claim 16 , wherein the least one access line includes:
a first access line coupled to the first transistor; and a second access line coupled to the second transistor.

18 . The apparatus of claim 17 , wherein the first and second access lines are separated from each other.

19 . The apparatus of claim 18 , wherein the first and second access lines are coupled to each other.

20 . The apparatus of claim 16 , wherein the first channel region is to conduct current between the first data line and the conductive region during an operation performed on the memory cell.

Assignees

• Micron Technology Inc

Inventors

• Pulugurtha Srinivas
• Ramaswamy Durai Vishak Nirmal

Classifications

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• G11C11/408

  Address circuits · CPC title

• H10B12/01

  Manufacture or treatment · CPC title