Semiconductor memory device and manufacturing method of semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2022399364-A1
Application number	US-202117538191-A
Country	US
Kind code	A1
Filing date	Nov 30, 2021
Priority date	Jun 15, 2021
Publication date	Dec 15, 2022
Grant date	—

Abstract

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a source structure; and a gate stacked structure disposed over the source structure, the gate stacked structure having a cell array region and a contact region with a stepped shape, wherein a roughness of a first sidewall of the cell array region of the gate stacked structure is greater than that of a second sidewall of the contact region of the gate stacked structure.

2 . The semiconductor memory device of claim 1 , wherein the first sidewall extends sinuously, and
wherein the second sidewall extends straight.

3 . The semiconductor memory device of claim 1 , wherein the first sidewall and the second sidewall are coupled to each other.

4 . The semiconductor memory device of claim 1 , further comprising:
a channel structure connected to the source structure, the channel structure passing through the gate stacked structure; and a memory pattern between the channel structure and the gate stacked structure.

5 . The semiconductor memory device of claim 1 , further comprising:
an insulating layer extending along the first sidewall and the second sidewall of the gate stacked structure; and a conductive source contact spaced apart from the gate stacked structure with the insulating layer therebetween, the conductive source contact being connected to the source structure.

6 . The semiconductor memory device of claim 1 , wherein the source structure includes a doped semiconductor layer.

7 . The semiconductor memory device of claim 1 , wherein the gate stacked structure includes interlayer insulating layers and conductive patterns that are stacked alternately with each other over the source structure.

8 . A semiconductor memory device, comprising:
a first gate stacked structure and a second gate stacked structure that are spaced apart from each other; a vertical structure between the first gate stacked structure and the second gate stacked structure, the vertical structure comprising a first portion and a second portion; and a plurality of cell plugs passing through the first gate stacked structure and the second gate stacked structure to be adjacent to both sides of the first portion of the vertical structure, wherein the first portion of the vertical structure includes depressions and protrusions that face the plurality of cell plugs, and wherein the second portion of the vertical structure is formed in a straight shape.

9 . The semiconductor memory device of claim 8 , further comprising a plurality of conductive gate contacts disposed to be adjacent to both sides of the second portion of the vertical structure and in contact with the first gate stacked structure and the second gate stacked structure.

10 . The semiconductor memory device of claim 8 , wherein each of the first gate stacked structure and the second gate stacked structure includes a contact region with a stepped shape, and
wherein the second portion of the vertical structure is disposed between the contact region with the stepped shape of the first gate stacked structure and the contact region with the stepped shape of the second gate stacked structure.

11 . The semiconductor memory device of claim 8 , further comprising a source structure disposed below the first gate stacked structure and the second gate stacked structure, the source structure connected to the plurality of cell plugs.

12 . The semiconductor memory device of claim 11 , wherein the vertical structure further comprises:
an insulating layer extending along a sidewall of each of the first gate stacked structure and the second gate stacked structure; and a conductive source contact spaced apart from the first gate stacked structure and the second gate stacked structure with the insulating layer therebetween, the conductive source contact being connected to the source structure.

13 . The semiconductor memory device of claim 11 ,
wherein the source structure includes a doped semiconductor layer.

14 . The semiconductor memory device of claim 11 , wherein each of the first gate stacked structure and the second gate stacked structure includes interlayer insulating layers and conductive patterns that are stacked alternately with each other over the source structure.

15 . The semiconductor memory device of claim 11 , wherein the plurality of cell plugs comprise:
channel structures passing through the first gate stacked structure and the second gate stacked structure, the channel structure being in contact with the source structure; and memory patterns surrounding sidewalls of the channel structures.

16 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a stacked structure with a cell array region and a contact region; forming a hole group with a plurality of channel holes and a plurality of auxiliary holes, the plurality of channel holes and the plurality of auxiliary holes passing through the cell array region of the stacked structure and being arranged in a plurality of rows; forming a memory layer along a surface of each of the plurality of channel holes; forming a channel structure on the memory layer; forming a first trench that passes through the contact region of the stacked structure; and removing a part of the stacked structure through the plurality of auxiliary holes and the first trench such that a slit is formed, wherein the plurality of auxiliary holes and the first trench are coupled in the slit.

17 . The method of claim 16 , wherein the plurality of channel holes include a plurality of first channel holes that are arranged along a first row in a first direction and a plurality of second channel holes that are arranged along a second row in the first direction,
wherein the plurality of auxiliary holes include a plurality of first auxiliary holes that are arranged along a third row that is adjacent to the first row in the first direction and a plurality of second auxiliary holes that are arranged along a fourth row that is adjacent to the second row in the first direction, and wherein the third row and the fourth row are disposed between the first row and the second row.

18 . The method of claim 17 , wherein a distance between each of the plurality of first auxiliary holes and each of the plurality of second auxiliary holes is smaller than each of a distance between each of the plurality of first auxiliary holes and each of the plurality of first channel holes and a distance between each of the plurality of second auxiliary holes and each of the plurality of second channel holes.

19 . The method of claim 17 , wherein, in a second direction in which the plurality of rows are arranged, a width of each of the plurality of first and second auxiliary holes is smaller than a width of each of the plurality of first and second channel holes.

20 . The method of claim 16 , wherein a distance between the plurality of auxiliary holes is smaller than a distance between the plurality of channel holes.

21 . The method of claim 16 , wherein, when the first trench is formed, second trenches that pass through the contact region of the stacked structure to be adjacent to both sides of the first trench and a supporting hole that passes through the contact region of the stacked structure between the first trench and the second trench are formed.

22 . The method of claim 21 , further comprising:
forming a supporting pillar that fills the supporting hole and a vertical insulating structure

Assignees

• Sk Hynix Inc

Inventors

• Kim Jang Won
• Park Mi Seong
• Park In Su
• Jang Jung Shik
• Choi Won Geun

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L21/76895

  Electricity · mapped topic