Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9653474-B2
Application number	US-201514880656-A
Country	US
Kind code	B2
Filing date	Oct 12, 2015
Priority date	May 22, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A method for fabricating an electronic device including a semiconductor memory may include: forming a stack structure in which an interlayer dielectric layer and a material layer are alternately stacked on a substrate; forming a plurality of holes arranged to have a substantially constant interval while exposing the substrate by passing through the stack structure; forming a channel layer in a first hole of the plurality of holes; forming a dummy layer in a second hole of the plurality of holes; forming a mask pattern on a resultant structure including the dummy layer and the channel layer to expose an area extending in a first direction while overlapping the dummy layer arranged in the first direction; and forming a slit by etching the stack structure using the mask pattern as an etching barrier and removing the dummy layer.

First claim

What is claimed is:

1. A method for fabricating an electronic device including a semiconductor memory, comprising:
forming a stack structure in which an interlayer dielectric layer and a material layer are alternately stacked on a substrate;
forming a plurality of holes arranged to have a substantially constant interval while exposing the substrate by passing through the stack structure;
forming a channel layer in a first hole of the plurality of holes;
forming a dummy layer in a second hole of the plurality of holes;
forming a mask pattern on a resultant structure including the dummy layer and the channel layer to expose an area extending in a first direction while overlapping the dummy layer arranged in the first direction; and
forming a slit by etching the stack structure using the mask pattern as an etching barrier and removing the dummy layer.

2. The method of claim 1 , wherein, in a second direction crossing the first direction, a width of the area exposed by the mask pattern is smaller than a width of the dummy layer.

3. The method of claim 1 , wherein the slit includes convex parts having a relatively larger width in the second direction than concave parts having a relatively smaller width in the second direction.

4. The method of claim 3 , wherein the convex parts and the concave parts are alternately arranged along the first direction.

5. The method of claim 1 , wherein the plurality of holes are arranged to be positioned on a substantially straight line in the first direction, and are not positioned on the straight line and cross one another in the second direction.

6. The method of claim 5 , wherein the slit includes convex parts having a relatively larger width in the second direction than concave parts having a relatively smaller width in the second direction,
the concave parts are formed at positions respectively corresponding to a plurality of channel layers adjacent to the slit, and
the convex parts are formed at positions respectively corresponding to areas between the plurality of channel layers adjacent to the slit.

7. The method of claim 1 , wherein the dummy layer is formed of a material substantially equal to the interlayer dielectric layer or the material layer.

8. The method of claim 7 , wherein the etching of the stack structure and the removal of the dummy layer are simultaneously performed.

9. The method of claim 1 , wherein the etching of the stack structure for forming the slit and removal of the mask pattern are simultaneously performed.

10. The method of claim 7 , wherein the etching of the stack structure, the removal of the dummy layer, and removal of the mask pattern are simultaneously performed.

11. The method of claim 1 , further comprising:
forming a memory layer interposed between the channel layer and the material layer.

12. The method of claim 1 , further comprising, after the forming of the slit:
removing the material layer; and
filling a space, from which the material layer has been removed, with a conductive material.

13. The method of claim 1 , further comprising, after the forming of the slit:
forming a groove by removing the material layer; and
forming a metal layer along an inner surface of the groove.

14. The method of claim 13 , further comprising:
filling a remaining space of the groove with another metal layer,
wherein the metal layer is configured as a diffusion barrier.

15. The method of claim 1 , wherein the material layer includes a conductive material.

16. An electronic device including a semiconductor memory, wherein the semiconductor memory comprises:
a plurality of channel layers extending in a vertical direction from a substrate;
an interlayer dielectric layer and a gate electrode layer alternately stacked on the substrate along the channel layer;
a memory layer interposed between the channel layer and the gate electrode layer; and
a slit formed in a stack structure of the interlayer dielectric layer and the gate electrode layer and extending in a first direction,
wherein the slit includes first convex parts mirrored with second convex parts located across from the first convex parts, respectively, and
wherein the slit includes first concave parts mirrored with second concave parts located across from the second concave parts, respectively.

17. The electronic device of claim 16 , wherein a distance between the first convex parts and second convex parts is greater than a distance between the first concave parts and second concave parts.

18. The electronic device of claim 16 , further comprising:
a convex part including the first convex part and the second convex part;
a concave part including the first concave part and the second concave part,
wherein a plurality of the convex parts and a plurality of the concave parts are alternately arranged along the first direction.

19. An electronic device including a semiconductor memory, wherein the semiconductor memory comprises:
a plurality of channel layers extending in a vertical direction from a substrate;
an interlayer dielectric layer and a gate electrode layer alternately stacked on the substrate along the channel layer;
a memory layer interposed between the channel layer and the gate electrode layer; and
a slit formed in a stack structure of the interlayer dielectric layer and the gate electrode layer and extending in a first direction,
wherein the slit includes convex parts having a relatively larger width in a second direction crossing the first direction than concave parts having a relatively smaller width in the second direction.

20. The electronic device of claim 19 , wherein the convex parts and the concave parts are alternately arranged along the first direction.

21. The electronic device of claim 19 , wherein the plurality of channel layers are arranged to be positioned on a substantially straight line in the first direction, and are not positioned on the straight line and cross one another in the second direction.

22. The electronic device of claim 21 , wherein the concave parts are formed at positions respectively corresponding to the plurality of channel layers adjacent to the slit, and
the convex parts are formed at positions respectively corresponding to areas between the plurality of channel layers adjacent to the slit.

23. The electronic device according to claim 19 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

24. The electronic device according to claim 19 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and

Assignees

• Sk Hynix Inc

Inventors

• Yune Hyoung-Soon

Classifications

• G06F2212/313

  In storage device · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic