Contact structure and method of making

Patent metadata

Field	Value
Publication number	US-2022278040-A1
Application number	US-202117187143-A
Country	US
Kind code	A1
Filing date	Feb 26, 2021
Priority date	Feb 26, 2021
Publication date	Sep 1, 2022
Grant date	—

Abstract

A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.

First claim

1 . A semiconductor device comprising:
an insulating layer, wherein the insulating layer has a via opening and a conductive line opening; a via in the via opening, wherein the via comprises a first conductive material; and a conductive line in the conductive line opening, wherein the conductive line comprises:
a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and
a conductive fill comprising a second conductive material different from the first conductive material.

2 . The semiconductor device of claim 1 , wherein the first liner layer comprises tantalum nitride (TaN).

3 . The semiconductor device of claim 1 , wherein the first conductive material directly contacts the insulating layer.

4 . The semiconductor device of claim 1 , wherein the first conductive material comprises ruthenium or tungsten.

5 . The semiconductor device of claim 1 , wherein the conductive line further comprises a second liner layer between the first liner layer and the conductive fill.

6 . The semiconductor device of claim 5 , wherein the second liner layer comprises the first conductive material.

7 . The semiconductor device of claim 1 , wherein the first liner layer extends into the via opening.

8 . The semiconductor device of claim 1 , wherein the conductive fill extends into the via opening.

9 . The semiconductor device of claim 1 , wherein the first thickness is less than 50% of the second thickness.

10 . The semiconductor device of claim 1 , wherein a third thickness of the first liner layer along sidewalls of the insulating layer is equal to the second thickness.

11 - 15 . (canceled)

16 . A semiconductor device comprising:
an insulating layer, wherein the insulating layer has a via opening and a conductive line opening; a via in the via opening, wherein the via comprises a first conductive material; and a conductive line in the conductive line opening, wherein the conductive line comprises:
a first liner layer having a variable thickness,
a second liner layer over the first liner layer, and
a conductive fill comprising a second conductive material different from the first conductive material, wherein the first liner layer is between the second liner layer and the conductive fill.

17 . The semiconductor device of claim 16 , wherein the first liner layer extends into the via opening.

18 . The semiconductor device of claim 17 , wherein a first portion of the first liner layer contacting the via is thinner than a second portion of the first liner layer contacting the insulating layer.

19 . The semiconductor device of claim 16 , wherein the first conductive material comprises ruthenium.

20 . The semiconductor device of claim 16 , wherein the second liner layer directly contacts the conductive fill.

21 . A semiconductor device comprising:
an insulating layer, wherein the insulating layer has a via opening and a conductive line opening; a via in the via opening, wherein the via comprises a first conductive material; and a conductive line in the conductive line opening, wherein the conductive line comprises:
a first liner layer having a variable thickness,
a second liner layer over the first liner layer, wherein the second liner layer has a uniform thickness, and
a conductive fill comprising a second conductive material different from the first conductive material.

22 . The semiconductor device of claim 21 , wherein the first liner layer extends into the via opening.

23 . The semiconductor device of claim 21 , wherein the second liner layer directly contacts a top-most surface of the conductive fill.

24 . The semiconductor device of claim 21 , further comprising an etch stop layer over the insulating layer.

25 . The semiconductor device of claim 24 , wherein the second liner layer directly contacts the etch stop layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chin Shu-Cheng
• Liu Yao-Min
• Su Hung-Wen
• Chi Chih-Chien
• Lin Chi-Feng

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/084 Primary

  for dual-damascene structures · CPC title