Removal of stray ruthenium metal nuclei for selective ruthenium metal layer formation

Patent metadata

Field	Value
Publication number	US-2022254683-A1
Application number	US-202217573946-A
Country	US
Kind code	A1
Filing date	Jan 12, 2022
Priority date	Feb 5, 2021
Publication date	Aug 11, 2022
Grant date	—

Abstract

A method for removal of stray Ru metal nuclei for selective Ru metal layer formation includes depositing ruthenium (Ru) metal on a patterned substrate by vapor phase deposition, where a Ru metal layer is deposited on a surface of a metal layer and Ru metal nuclei are deposited on a surface of a dielectric layer. The method further includes removing the Ru metal nuclei by gas phase etching using an ozone (O3) gas exposure that forms volatile ruthenium oxide species by oxidation of the Ru metal nuclei, and repeating the depositing and removing steps at least once to increase a thickness of the Ru metal layer, where the depositing is interrupted before the Ru metal nuclei reach a critical size that results in formation of non-volatile ruthenium oxide species and incomplete removal of the Ru metal nuclei during the gas phase etching.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, the method comprising:
providing a patterned substrate containing a dielectric layer and a metal layer; depositing ruthenium (Ru) metal on the patterned substrate by vapor phase deposition, wherein a Ru metal layer is deposited on a surface of the metal layer and Ru metal nuclei are deposited on a surface of the dielectric layer; removing the Ru metal nuclei by gas phase etching using an ozone (O 3 ) gas exposure that forms volatile ruthenium oxide species by oxidation of the Ru metal nuclei; and repeating the depositing and removing steps at least once to increase a thickness of the Ru metal layer, wherein the depositing is interrupted before the Ru metal nuclei reach a critical size that results in formation of non-volatile ruthenium oxide species and incomplete removal of the Ru metal nuclei during the gas phase etching.

2 . The method of claim 1 , wherein the depositing and removing are performed at substantially the same substrate temperature.

3 . The method of claim 1 , wherein the depositing and removing are performed in a single process chamber.

4 . The method of claim 1 , wherein the patterned substrate is not exposed to air between the depositing and removing steps.

5 . The method of claim 1 , wherein the dielectric layer has a recessed feature and the metal layer is exposed in the recessed feature.

6 . The method of claim 1 , wherein dielectric layer contains a recessed feature that includes a trench having a first width, and a via containing the metal layer and having a second width that is less than the first width.

7 . The method of claim 6 , wherein the Ru metal layer fully fills the via.

8 . The method of claim 1 , wherein the Ru metal is deposited using a Ru 3 (CO) 12 precursor in a CO carrier gas.

9 . The method of claim 1 , wherein the metal layer contains Cu metal, Ru metal, Co metal, or W metal.

10 . The method of claim 1 , wherein the critical size of the Ru metal nuclei is less than about 4 nm.

11 . A method of forming a semiconductor device, the method comprising:
providing a patterned substrate containing a dielectric layer and a metal layer; depositing ruthenium (Ru) metal on the patterned substrate by vapor phase deposition, wherein a Ru metal layer is deposited on a surface of the metal layer and Ru metal nuclei are deposited on a surface of the dielectric layer; removing a portion of the Ru metal nuclei by gas phase etching using an ozone (O 3 ) gas exposure that forms volatile ruthenium oxide species by oxidation of the Ru metal nuclei; exposing the patterned substrate to a reducing gas containing H 2 gas that converts non-volatile ruthenium oxide species formed during the O 3 gas exposure to metallic Ru; and repeating the depositing, removing, and exposing steps at least once to increase a thickness of the Ru metal layer.

12 . The method of claim 11 , wherein the depositing and removing are performed at substantially the same substrate temperature.

13 . The method of claim 11 , wherein the depositing and removing are performed in the same process chamber.

14 . The method of claim 11 , wherein the removing and exposing steps are repeated at least once to fully remove the Ru metal nuclei before the depositing step is repeated.

15 . The method of claim 11 , wherein the steps of gas phase etching using an O 3 gas exposure and the exposing the patterned substrate to the reducing gas containing H 2 gas have at least partial temporal overlap.

16 . The method of claim 11 , wherein the dielectric layer has a recessed feature and the metal layer is exposed in the recessed feature.

17 . The method of claim 11 , wherein dielectric layer contains a recessed feature that includes a trench having a first width, and a via containing the metal layer and having a second width that is less than the first width.

18 . The method of claim 17 , wherein the Ru metal layer fully fills the via.

19 . The method of claim 11 , wherein the Ru metal is deposited using a Ru 3 (CO) 12 precursor in a CO carrier gas.

20 . The method of claim 11 , wherein the metal layer contains Cu metal, Ru metal, Co metal, or W metal.

Assignees

• Tokyo Electron Ltd
• Univ Colorado Regents

Inventors

• Zandi Omid
• Faguet Jacques
• Zywotko David
• George Steven M

Classifications

• H10W20/0595

  by using multiple deposition steps separated by etching steps · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/055

  by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition · CPC title

• H10W20/4432

  the principal metal being a noble metal, e.g. gold · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title