Overhang reduction using pulsed bias
US-2021391176-A1 · Dec 16, 2021 · US
by using multiple deposition steps separated by etching steps
by using multiple deposition steps separated by etching steps · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W20/0595 |
| Official title | {by using multiple deposition steps separated by etching steps} |
| Display label | by using multiple deposition steps separated by etching steps |
| Total patents | 187 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 7 |
| 2016 | 4 |
| 2017 | 9 |
| 2018 | 8 |
| 2019 | 5 |
| 2020 | 10 |
| 2021 | 21 |
| 2022 | 38 |
| 2023 | 22 |
| 2024 | 30 |
| 2025 | 25 |
| 2026 | 8 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Interconnect Structure with Partial Sidewall Liner
US-2021375671-A1 · Dec 2, 2021 · US
Semiconductor device and apparatus of manufacturing the same
US-11189633-B2 · Nov 30, 2021 · US
Tungsten feature fill
US-2021327754-A1 · Oct 21, 2021 · US
Methods and apparatus for forming dual metal interconnects
US-2021320064-A1 · Oct 14, 2021 · US
Atomic layer etching of tungsten for enhanced tungsten deposition fill
US-2021305059-A1 · Sep 30, 2021 · US
Multi-metal interconnects for semiconductor device structures
US-2021305160-A1 · Sep 30, 2021 · US
Atomic layer etch of tungsten for enhanced tungsten deposition fill
US-11069535-B2 · Jul 20, 2021 · US
Fin field effect transistor device structure and method for forming the same
US-2021126129-A1 · Apr 29, 2021 · US
Methods for filling a gap feature on a substrate surface and related semiconductor structures
US-2021125832-A1 · Apr 29, 2021 · US
Fill process optimization using feature scale modeling
US-10977405-B2 · Apr 13, 2021 · US
Contact Features and Methods of Fabricating the Same in Semiconductor Devices
US-2021098364-A1 · Apr 1, 2021 · US
Method of bottom-up metallization in a recessed feature
US-2021082750-A1 · Mar 18, 2021 · US
Semiconductor device
US-2021066289-A1 · Mar 4, 2021 · US
Metal Contact Structure and Method of Forming the Same in a Semiconductor Device
US-2021050254-A1 · Feb 18, 2021 · US
Decoupled via fill
US-10903114-B2 · Jan 26, 2021 · US
Methods and apparatus for forming dual metal interconnects
US-2021020569-A1 · Jan 21, 2021 · US
Metal contact structure and method of forming the same in a semiconductor device
US-10825724-B2 · Nov 3, 2020 · US
Semiconductor device and apparatus of manufacturing the same
US-2020303409-A1 · Sep 24, 2020 · US
Method for forming a metal gapfill
US-2020303250-A1 · Sep 24, 2020 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W20/0595?
- CPC H10W20/0595 is the Cooperative Patent Classification code for “by using multiple deposition steps separated by etching steps.”
- How many patents are filed under CPC H10W20/0595 (by using multiple deposition steps separated by etching steps)?
- Our database includes 187 publications tagged with this CPC code.
- Is patent activity under CPC H10W20/0595 growing?
- Publication counts under this code: 30 in 2024 vs 25 in 2025 (latest complete years).