Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022173253-A1
Application number	US-202117327725-A
Country	US
Kind code	A1
Filing date	May 23, 2021
Priority date	Dec 1, 2020
Publication date	Jun 2, 2022
Grant date	—

Abstract

A semiconductor device includes; an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern. The semiconductor patterns includes a first semiconductor pattern and a second semiconductor pattern. The gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern. A width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern, wherein the semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern, the gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern, and a width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

2 . The semiconductor device of claim 1 , wherein the source/drain pattern is an N-type source/drain pattern and includes a bottom surface contacting the substrate.

3 . The semiconductor device of claim 1 , wherein the source/drain pattern includes a protrusion that protrudes in a direction towards the gate electrode.

4 . The semiconductor device of claim 3 , wherein the first part has a recessed sidewall, the recessed sidewall faces the protrusion, and the recessed sidewall has a profile that conforms with a profile of the protrusion.

5 . The semiconductor device of claim 1 , wherein the width of the lower portion is greater than the width of the upper portion.

6 . The semiconductor device of claim 5 , wherein a minimum width of the second part is less than the width of the middle portion of the first part.

7 . The semiconductor device of claim 6 , wherein
the semiconductor patterns further include a third semiconductor pattern on the second semiconductor pattern, the gate electrode further includes a third part between the second semiconductor pattern and the third semiconductor pattern, and a minimum width of the third part is less than the minimum width of the second part.

8 . The semiconductor device of claim 1 , wherein each of the first part and the second part includes:
a contact segment adjacent to the source/drain pattern and having a recessed sidewall; and an extension segment extending from the contact segment in a direction away from the recessed sidewall and including a protruding pattern that protrudes in the direction perpendicular to a top surface of the substrate.

9 . The semiconductor device of claim 8 , wherein a thickness of the contact segment is less than a thickness of the extension segment.

10 . The semiconductor device of claim 1 , further comprising:
an active contact coupled to the source/drain pattern and including an upper dielectric pattern; and a gate contact coupled to the gate electrode.

11 . A semiconductor device, comprising:
an active pattern on a substrate; an N-type source/drain pattern on the active pattern including a bottom surface contacting the substrate; a channel pattern connected to the N-type source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, wherein the semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern; and a gate electrode extending across the channel pattern and including a first part between the substrate and the first semiconductor pattern, wherein the N-type source/drain pattern includes a protrusion that protrudes in a direction toward the gate electrode, the first part includes a recessed sidewall, and the recessed sidewall faces the protrusion and has a profile that conforms to a profile of the protrusion.

12 . The semiconductor device of claim 11 , wherein the gate electrode further includes a second part between the first semiconductor pattern and the second semiconductor pattern, and
a minimum width of the first part is greater than a minimum width of the second part.

13 . The semiconductor device of claim 12 , wherein each of the first part and the second part includes:
a contact segment adjacent to the N-type source/drain pattern and including a recessed sidewall; and an extension segment extending from the contact segment in a direction away from the recessed sidewall, and including a protruding pattern that protrudes in a direction perpendicular to a top surface of the substrate.

14 . The semiconductor device of claim 11 , wherein width of the first part varies with depth of the first part, decreasing to a minimum value and then increasing as the depth extends in a direction perpendicular to a top surface of the substrate.

15 . The semiconductor device of claim 14 , wherein the first part includes a lower portion having a first width, a middle portion having a second width, and an upper part having a third width greater than the second width and less than the first width.

16 . A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region adjacent to one another in a first direction; a first active pattern on the PMOSFET region, a first source/drain pattern on the first active pattern, and a first channel pattern connected to the first source/drain pattern and including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern spaced apart in a first vertical stack; a second active pattern on the NMOSFET region, a second source/drain pattern on the second active pattern, and a second channel pattern on the second source/drain pattern and including the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern spaced apart in a second vertical stack; a first gate electrode extending in the first direction across the first channel pattern and including a first part between the substrate and the first semiconductor pattern, a second part between the first semiconductor pattern and the second semiconductor pattern, a third part between the second semiconductor pattern and the third semiconductor pattern, and a fourth part on the third semiconductor pattern; a second gate electrode extending in the first direction across the second channel pattern and including a first part between the substrate and the first semiconductor pattern, a second part between the first semiconductor pattern and the second semiconductor pattern, a third part between the second semiconductor pattern and the third semiconductor pattern, and a fourth part on the third semiconductor pattern; a first gate dielectric layer between the first channel pattern and the first gate electrode; a second gate dielectric layer between the second channel pattern and the second gate electrode; a first gate spacer on a sidewall of the first gate electrode; a second gate spacer on a sidewall of the second gate electrode; a first gate capping pattern on a top surface of the first gate electrode; a second gate capping pattern on a top surface of the second gate electrode; a first interlayer dielectric layer on the first gate capping pattern and the second gate capping pattern; active contacts penetrating the first interlayer dielectric layer and correspondingly coupled to the first source/drain pattern and the second source/drain pattern; gate contacts penetrating the first interlayer dielectric layer and correspondingly coupled to the first gate electrode and the second gate electrode; a second interlayer dielectric layer on the first interlayer dielectric layer; a first metal layer in the second

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yeom Donghyuk
• Kim Junkyum
• Lee Kwan Heum
• Park Seonghwa
• Seo Sohyun

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title