SRAM cells with vertical gate-all-around MOSFETs

Patent metadata

Field	Value
Publication number	US-10522554-B2
Application number	US-201816214818-A
Country	US
Kind code	B2
Filing date	Dec 10, 2018
Priority date	Sep 15, 2014
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A Static Random Access Memory (SRAM) cell includes a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate as a second source/drain region. A first isolated active region is in the SRAM cell and acts as the bottom plate of the first pull-down transistor and the bottom plate of the first pass-gate transistor. A second isolated active region is in the SRAM cell and acts as the bottom plate of the second pull-down transistor and the bottom plate of the second pass-gate transistor.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a semiconductor substrate;
a plurality of isolation regions extending into the semiconductor substrate, wherein the plurality of isolation regions separate portions of the semiconductor substrate into a plurality of active regions comprising:
a continuous active region;
a first plurality of active regions aligned to a first straight line that is parallel to a lengthwise direction of the continuous active region; and
a second plurality of active regions aligned to a second straight line that is parallel to the lengthwise direction of the continuous active region, wherein the first straight line and the second straight line are on opposite sides of the continues active region; and

an array of Static Random Access Memory (SRAM) cells comprising a column, wherein the continuous active region continuously extends into all SRAM cells in the column, and each of SRAM cells in the column comprises one of the first plurality of active regions and one of the second plurality of active regions.

2. The integrated circuit device of claim 1 , wherein each of the first plurality of active regions comprises a source/drain region of a pass-gate transistor and a source/drain region of a pull-down transistor of an SRAM cell in the column.

3. The integrated circuit device of claim 1 , wherein the column of SRAM cells comprises an SRAM cell, and the SRAM cell comprises a first boundary and a second boundary parallel to each other, and one of the first plurality of active regions is in the SRAM cell, and is spaced apart from both the first boundary and the second boundary.

4. The integrated circuit device of claim 3 , wherein the SRAM cell further comprises a third boundary and a fourth boundary parallel to each other, and the one of the first plurality of active regions is further spaced apart from both the third boundary and the fourth boundary.

5. The integrated circuit device of claim 1 , wherein each of the SRAM cells of the array comprises a plurality of Vertical Gate-All-Around (VGAA) transistors.

6. The integrated circuit device of claim 5 , wherein in a top view of the integrated circuit device, channel regions of the plurality of VGAA transistors are limited inside boundaries of the first plurality of active regions, the second plurality of active regions, or the continuous active region.

7. The integrated circuit device of claim 1 , wherein each of the first plurality of active regions is fully encircled by one of the plurality of isolation regions.

8. The integrated circuit device of claim 1 , wherein the plurality of isolation regions that encircle the first plurality of active regions are continuously interconnected.

9. The integrated circuit device of claim 1 , wherein the continuous active region is a CVdd power rail.

10. The integrated circuit device of claim 1 , wherein the continuous active region is a CVss power rail.

11. An integrated circuit device comprising:
a semiconductor substrate;
a continuous active region in the semiconductor substrate;
a Static Random Access Memory (SRAM) cell array comprising a column of SRAM cells, wherein each SRAM cell in the column of SRAM cells comprises:
a first pull-up transistor and a second pull-up transistor, wherein a source/drain region of each of the first pull-up transistor and the second pull-up transistor is in the continuous active region;
a first active region and a second active region in the semiconductor substrate;
a first pass-gate transistor and a second pass-gate transistor; and
a first pull-down transistor and a second pull-down transistor, wherein in a top view of the SRAM cell, each of source regions, drain regions, and channels of the first pull-down transistor and the second pull-down transistor is in one of the first active region and the second active region, and the first active region and the second active region are spaced apart from neighboring SRAM cells in the SRAM cell array.

12. The integrated circuit device of claim 11 , wherein the each SRAM cell in the column of SRAM cells comprises:
a first boundary and a second boundary opposite to each other; and
a third boundary and a fourth boundary opposite to each other, wherein the first boundary and the second boundary are perpendicular to the third boundary and the fourth boundary, and the first active region and the second active region are spaced apart from the first boundary, the second boundary, the third boundary, and the fourth boundary.

13. The integrated circuit device of claim 12 , wherein no active region in any SRAM cell in the column of SRAM cells extends to the third boundary and the fourth boundary.

14. The integrated circuit device of claim 11 further comprising an isolation region extending into the semiconductor substrate, wherein in a top view of the SRAM cell array, the isolation region encircles each of the first active region and the second active region, and the first active region and the second active region are spaced apart from each other by the isolation region.

15. The integrated circuit device of claim 11 , wherein the each SRAM cell in the column of SRAM cells further comprises:
a pull-up transistor; and
a butted contact comprising a first portion over and electrically connecting to the first active region, and a second portion overlapping and electrically connecting to a gate electrode of the pull-up transistor.

16. The integrated circuit device of claim 11 , wherein isolation regions in the column of SRAM cells are separated by the continuous active region into two continuous regions.

17. An integrated circuit device comprising:
a Static Random Access Memory (SRAM) cell comprising:
a P-well region;
a first active region extending into the P-well region, wherein the first active region extends to opposite boundaries of the SRAM cell;
a first N-well region and a second N-well region on opposite sides of the P-Well region;
a second active region in the first N-well region;
a third active region in the second N-well region;

a first pull-up transistor and a second pull-up transistor, each comprising:
a first source/drain region in the first active region; and
a channel region and a second source/drain region overlapping the first source/drain region;

a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor; and
a first pass-gate transistor and a second pass-gate transistor, wherein each of the first and the second pull-down transistors and the first and the second pass-gate transistors comprises a first source/drain region in one of the second active region and the third active region, a channel over the first source/drain region, and a second source/drain region over the channel.

18. The integrated circuit device of claim 17 further comprising:
a semiconductor substrate; and
Shallow Trench Isolation (STI) regions extending into the semiconductor substrate, wherein the STI regions separate portions of the semiconductor substrate into the first active region, the second active region, and the third active region.

19. The integrated circuit device of claim 17 , wherein the first active region and the second active region are spaced apart from all boundaries of the SRAM cell, and the third active region extends to opposite boundaries of the SRAM cell.

20. The integrated circuit device of claim 17 , wherein the first active region is a CVSS power rail of the SRAM cell.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic