Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2022077041-A1
Application number	US-202117405603-A
Country	US
Kind code	A1
Filing date	Aug 18, 2021
Priority date	Sep 9, 2020
Publication date	Mar 10, 2022
Grant date	—

Abstract

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

First claim

1 . A semiconductor package, comprising:
a first redistribution substrate; and a first semiconductor device on the first redistribution substrate, wherein the first redistribution substrate includes:
a first dielectric layer that includes a first hole;
an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer;
an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole;
a wetting layer between the external connection terminal and the under-bump; and
a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

2 . The semiconductor package of claim 1 , wherein an inner sidewall of the first hole makes a first angle with the bottom surface of the first dielectric layer,
wherein the first angle ranges from about 45° to about 90°.

3 . The semiconductor package of claim 1 , wherein the external connection terminal includes:
a first terminal part in the first hole; and a second terminal part that protrudes outwardly from the bottom surface of the first dielectric layer, wherein a sidewall of the first terminal part makes a first angle with a top surface of the second terminal part, wherein the first angle ranges from about 45° to about 90°.

4 . The semiconductor package of claim 1 , wherein the external connection terminal includes:
a first terminal part in the first hole; and a second terminal part that protrudes outwardly from the bottom surface of the first dielectric layer, wherein a width of the second terminal part is greater than a width of the first terminal part.

5 . The semiconductor package of claim 1 , wherein a sidewall of the first bump part makes a first angle with a bottom surface of the second bump part,
wherein the first angle ranges from about 90° to about 135°.

6 . The semiconductor package of claim 1 , wherein a width of the second bump part is greater than a width of the first bump part.

7 . The semiconductor package of claim 1 , wherein a sidewall of the external connection terminal, a sidewall of the wetting layer, and a sidewall of the first barrier/seed layer are aligned with each other.

8 . The semiconductor package of claim 1 , wherein the first redistribution substrate further includes:
a second dielectric layer that covers the first dielectric layer and the second bump part of the under-bump; and a first redistribution pattern that penetrates the second dielectric layer and is connected to the under-bump, wherein the second bump part is in direct contact with the second dielectric layer.

9 . The semiconductor package of claim 8 , wherein the first redistribution pattern includes a via part that penetrates the second dielectric layer and a line part that protrudes onto the second dielectric layer,
wherein a width of the via part is less than a width of the first bump part.

10 . The semiconductor package of claim 1 , wherein the first redistribution substrate further includes:
a second dielectric layer that covers the first dielectric layer and the second bump part of the under-bump; and a metal oxide layer between the second bump part and the second dielectric layer; and a void region between the second bump part and the metal oxide layer.

11 . A semiconductor package, comprising:
a first redistribution substrate; and a first semiconductor device on the first redistribution substrate, wherein the first redistribution substrate includes:
a first dielectric layer that includes a first hole;
an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer; and
an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole,
wherein an inner sidewall of the first hole makes a first angle with the bottom surface of the first dielectric layer, wherein the first angle ranges from about 45° to about 90°.

12 . The semiconductor package of claim 11 , wherein the first redistribution substrate further includes:
a wetting layer between the external connection terminal and the under-bump; and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

13 . The semiconductor package of claim 11 , wherein a sidewall of the first bump part makes a second angle with a bottom surface of the second bump part,
wherein the second angle ranges from about 90° to about 135°.

14 . The semiconductor package of claim 12 , wherein a sidewall of the external connection terminal, a sidewall of the wetting layer, and a sidewall of the first barrier/seed layer are aligned with each other.

15 . The semiconductor package of claim 11 , wherein the first redistribution substrate further includes:
a second dielectric layer that covers the first dielectric layer and the second bump part of the under-bump; and a first redistribution pattern that penetrates the second dielectric layer and is connected to the under-bump, wherein the second bump part is in direct contact with the second dielectric layer.

16 . The semiconductor package of claim 11 , wherein the first redistribution substrate further includes:
a second dielectric layer that covers the first dielectric layer and the second bump part of the under-bump; and a metal oxide layer between the second bump part and the second dielectric layer; and a void region between the second bump part and the metal oxide layer.

17 . A semiconductor package, comprising:
a first redistribution substrate; a first semiconductor device on the first redistribution substrate; and a mold layer that covers the first semiconductor device and the first redistribution substrate, wherein the first redistribution substrate includes:
a first dielectric layer that includes a first hole;
an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer;
an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole;
a wetting layer between the external connection terminal and the under-bump;
a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer;
a second dielectric layer that covers the under-bump and the first dielectric layer; and
a first redistribution pattern that penetrates the second dielectric layer and is connected to the under-bump,
wherein the external connection terminals includes:
a first terminal part in the first hole; and
a second terminal part that protrudes outwardly from the bottom surface of the first dielectric layer,
wherein a sidewall of the first terminal part makes a first angle with a top surface of the second terminal part, wherein the first angle ranges from about 45° to about 90°.

18 . The semiconductor package of claim 17 , wherein a sidewall of the first bump part makes a second angle with a bottom surface of the second bump part,
wherein the second angle ranges from about 90° to about 135°.

19 . The semiconductor package of claim 17 , wherein a sidewall of the external connection terminal, a sidewall of the wetting layer, and a sidewall of the first barrier/

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Gwangjae
• Park Jung-Ho
• Lee Seokhyun
• Yoon Yaejung

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/722

  between stacked chips · CPC title