Package structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-10014260-B2
Application number	US-201615347912-A
Country	US
Kind code	B2
Filing date	Nov 10, 2016
Priority date	Nov 10, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.

First claim

What is claimed is:

1. A method for forming a package structure, comprising:
providing a carrier substrate;
forming a conductive layer over the carrier substrate;
forming a passivation layer over the conductive layer, wherein the passivation layer comprises openings that expose portions of the conductive layer;
bonding integrated circuit dies to the portions of the conductive layer through bumps, wherein there is a space between the integrated circuit dies and the passivation layer;
filling the space with a first molding compound, wherein the first molding compound surrounds the bumps and the integrated circuit dies;
forming a second molding compound capping the first molding compound and the integrated circuit dies, wherein the passivation layer has a sidewall that is covered by the second molding compound; and
cutting the first molding compound and the passivation layer to form the package structure, wherein the package structure is separated from the second molding compound.

2. The method for forming a package structure as claimed in claim 1 , wherein the integrated circuit die has an active surface, which is coupled to the bumps, and a non-active surface, and wherein the first molding compound has a portion between the non-active surface and the second molding compound.

3. The method for forming a package structure as claimed in claim 2 , further comprising removing the second molding compound and the portion of the first molding compound until the non-active surface is exposed, wherein the sidewall of the passivation layer stays covered by the second molding compound during the removal of the second molding compound and the portion of the first molding compound.

4. The method for forming a package structure as claimed in claim 1 , wherein the first molding compound is formed by an immersion molding process, and the second molding compound is formed by a compression molding process.

5. The method for forming a package structure as claimed in claim 1 , further comprising:
removing the carrier substrate after the filling of the space;
reversing the integrated circuit dies so that the integrated circuit dies are supported by the first molding compound and the second molding compound; and
forming second bumps after the reversal of the integrated circuit dies, wherein the second bumps are electrically connected to the integrated circuit dies through the conductive layer and the bumps.

6. The method for forming a package structure as claimed in claim 5 , further comprising:
forming a second passivation layer over the carrier substrate before the formation of the conductive layer, wherein the second passivation layer comprises second openings;
forming a second conductive layer over the second passivation layer, wherein the second conductive layer has portions filling the second openings, and the portions of the second conductive layer are exposed after the removal of the carrier substrate; and
recessing the exposed portions of the second conductive layer in the second openings before the formation of the second bumps, wherein the second bumps fill the second openings to electrically connect to the second conductive layer, and wherein the second openings gradually shrink along a direction from the integrated circuit dies towards the second bumps.

7. A method for forming a package structure, comprising:
providing a carrier substrate;
forming a conductive layer over the carrier substrate;
forming a passivation layer over the conductive layer, wherein the passivation layer comprises openings that expose portions of the conductive layer;
bonding an integrated circuit die to the portions of the conductive layer through connectors, wherein the integrated circuit die has an active surface, which is coupled to the connectors, and a non-active surface, and wherein the passivation layer has a sidewall and a top surface, the top surface of the passivation layer is facing the active surface of the integrated circuit die;
forming a first package layer covering the passivation layer and the non-active surface to surround the connectors and the integrated circuit die, wherein the first package layer is retracted inwardly from the sidewall of the passivation layer; and
forming a second package layer covering the first package layer, wherein the second package layer extends to the sidewall of the passivation layer.

8. The method for forming a package structure as claimed in claim 7 , wherein the second package layer further extends along the sidewall of the passivation layer to cover and surround the sidewall of the passivation layer.

9. The method for forming a package structure as claimed in claim 7 , further comprising thinning the first and second package layers, wherein the sidewall of the passivation layer is covered by the second package layer during the thinning of the first and second package layers.

10. The method for forming a package structure as claimed in claim 7 , wherein the connectors comprise a first bump and a second bump between the integrated circuit die and the first bump, and wherein the first bump is coupled to the conductive layer before bonding the integrated circuit die, and the second bump is coupled to the active surface before bonding the integrated circuit die.

11. The method for forming a package structure as claimed in claim 7 , wherein the second package layer has a coefficient of thermal expansion, which is greater than that of the first package layer.

12. The method for forming a package structure as claimed in claim 7 , wherein there is a space between the integrated circuit die and the passivation layer, and the method further comprises filling the space with a third package layer before the formation of the first and second package layers.

13. The method for forming a package structure as claimed in claim 12 , wherein the first, second and third package layers respectively comprise fillers having a first size, a second size and a third size, and the second size is greater than the first size and the third size.

14. A method for forming a package structure, comprising:
forming a first redistribution layer and a second redistribution layer over a carrier substrate;
forming a passivation layer covering the second redistribution layer;
bonding an integrated circuit die to the second redistribution layer through bumps;
forming a first package layer covering the passivation layer and surrounding the bumps and the integrated circuit die, wherein the first package layer is spaced apart from an edge of the passivation layer;
forming a second package layer covering and surrounding the first package layer and the edge of the passivation layer;
removing the carrier substrate after the formation of the second package layer; and
thinning the first package layer and the second package layer to expose the integrated circuit die.

15. The method for forming a package structure as claimed in claim 14 , wherein the second package layer has a larger area than the carrier substrate.

16. The method for forming a package structure as claimed in claim 14 , wherein the first redistribution layer comprises a conductive layer and a seed layer, and wherein the seed layer becomes exposed after the removal of the carrier substrate, and the conductive layer remains covered by the seed layer after the removal of the carrier substrate.

17. The method for forming a package structure as claimed in claim 16 , further comprising:
etching the seed layer to expose the conductive layer; and
forming a connector adjoining the conductive layer and the seed layer after the e

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Yi-Da
• Lin Cheng-Ping
• Lin Wei-Hung
• Lin Chih-Wei
• Cheng Ming-Da
• Hsieh Ching-Hua
• Liu Chung-Shi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title