Structure for stacked logic performance improvement

Patent metadata

Field	Value
Publication number	US-2017154850-A1
Application number	US-201615143950-A
Country	US
Kind code	A1
Filing date	May 2, 2016
Priority date	Nov 30, 2015
Publication date	Jun 1, 2017
Grant date	—

Abstract

In some embodiments, the present disclosure relates to an integrated chip (IC) having a back-side through-silicon-via (BTSV) with a direct physical connection between a metal interconnect layer and a back-side conductive bond pad. The IC has metal interconnect layers arranged within an inter-level dielectric structure disposed onto a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate, and a conductive bond pad is arranged over the dielectric layer. A BTSV extends from one of the metal interconnect layers through the substrate and the dielectric layer to the conductive bond pad. A conductive bump is arranged onto the conductive bond pad, which has a substantially planar lower surface extending from over the BTSV to below the conductive bump. Directly connecting the conductive bond pad to the BTSV reduces a size of the conductive bond thereby improving a routing capability of the conductive bond pad.

First claim

1 . An integrated chip, comprising:
a plurality of metal interconnect layers arranged within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate; a dielectric layer arranged along a back-side of the substrate; a conductive bond pad arranged over the dielectric layer; a back-side through-substrate-via (BTSV) extending from one of the plurality of metal interconnect layers through the substrate and the dielectric layer to the conductive bond pad, wherein the conductive bond pad extends past opposing sides of the BTSV; and a conductive bump arranged over the conductive bond pad at a location laterally separated from an outermost sidewall of the BTSV facing in direction of the conductive bump, wherein the conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump.

2 . The integrated chip of claim 1 , further comprising:
a high-k dielectric layer contacting the back-side of the substrate, wherein the high-k dielectric layer is vertically arranged between the conductive bond pad and the dielectric layer and the substrate.

3 . The integrated chip of claim 1 , further comprising:
a high-k dielectric layer vertically arranged between the dielectric layer and the substrate, wherein the BTSV extends through the high-k dielectric layer.

4 . The integrated chip of claim 1 , wherein the BTSV has smooth sidewalls that continuously extend between the one of the plurality of metal interconnect layers and the conductive bond pad.

5 . The integrated chip of claim 1 ,
wherein the plurality of metal interconnect layers comprise a first metal interconnect wire and a thicker, second metal interconnect wire that is separated from the substrate by the first metal interconnect wire; and wherein the BTSV has a first surface facing the first metal interconnect wire and a second surface facing the conductive bond pad, wherein the first surface has a smaller width than the second surface.

6 . The integrated chip of claim 1 , further comprising:
a passivation layer arranged over the dielectric layer and the conductive bond pad; and an under bump metallurgy (UBM) layer extending from over the passivation layer to within an opening within the passivation layer, wherein the UBM layer is positioned between the conductive bond pad and the conductive bump.

7 . The integrated chip of claim 1 , wherein the conductive bond pad has a first segment extending in a first direction and a second segment extending in a second direction perpendicular to the first direction, wherein the conductive bump is arranged over the second segment at a location that is separated from the first segment in the second direction.

8 . The integrated chip of claim 7 , wherein the BTSV contacts the first segment of the conductive bond pad.

9 . The integrated chip of claim 1 , further comprising:
a BTSV liner arranged along sidewalls of the BTSV to separate the BTSV from the substrate.

10 . The integrated chip of claim 1 , further comprising:
one or more additional BTSV arranged in parallel to the BTSV between the one of the plurality of metal interconnect layers and the conductive bond pad.

11 . The integrated chip of claim 1 , further comprising:
a buffer layer separated from the substrate by the dielectric layer and a high-k dielectric layer, wherein the BTSV has smooth sidewalls that extend through the dielectric layer, the buffer layer, and the high-k dielectric layer.

12 . An integrated chip, comprising:
a plurality of metal interconnect layers arranged within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate, wherein the plurality of metal interconnect layers comprise a first metal interconnect wire and a thicker, second metal interconnect wire that is separated from the substrate by the first metal interconnect wire; a high-k dielectric layer arranged onto a back-side of the substrate; a dielectric layer separated from the back-side of the substrate by the high-k dielectric layer; a conductive bond pad arranged over the dielectric layer; and a back-side through-substrate-via (BTSV) extending between the first metal interconnect wire and the conductive bond pad, wherein the BTSV has a first surface facing the first metal interconnect wire and a second surface facing the conductive bond pad, wherein the first surface has a smaller width than the second surface.

13 . The integrated chip of claim 12 , further comprising:
a passivation layer arranged over the dielectric layer and the conductive bond pad; an under bump metallurgy (UBM) layer extending from over the passivation layer to within an opening within the passivation layer; and a conductive bump arranged over the UBM layer, wherein the conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump.

14 . The integrated chip of claim 12 , wherein the BTSV has tapered sidewalls that continuously extend between the first metal interconnect wire and the conductive bond pad.

15 . The integrated chip of claim 12 , further comprising:
a buffer layer separated from the substrate by the dielectric layer and the high-k dielectric layer, wherein the BTSV has smooth sidewalls that extend through the dielectric layer, the buffer layer, and the high-k dielectric layer.

16 . The integrated chip of claim 12 , wherein the conductive bond pad has a first segment extending in a first direction and a second segment extending in a second direction perpendicular to the first direction, wherein a conductive bump is arranged over the second segment at a location that is separated from the first segment in the second direction.

17 . The integrated chip of claim 12 , wherein the conductive bond pad comprises aluminum.

18 . The integrated chip of claim 12 , wherein the BTSV comprises copper, aluminum, or tungsten.

19 . The integrated chip of claim 12 , wherein the BTSV has a width that is less than or equal to approximately 2.5 μm.

20 . A method of forming an integrated chip, comprising:
forming a plurality of metal interconnect layers within an inter-level dielectric (ILD) structure arranged along a front-side of a substrate, wherein the plurality of metal interconnect layers comprise a first metal interconnect wire and a thicker, second metal interconnect wire that is separated from the substrate by the first metal interconnect wire; forming a high-k dielectric layer onto a back-side of the substrate; forming a dielectric layer over the high-k dielectric layer; etching the dielectric layer, the high-k dielectric layer, the substrate, and the ILD structure to form a back-side through-substrate-via (BTSV) opening that extends to a position in contact with the first metal interconnect wire; depositing a conductive material within the BTSV opening after forming the plurality of metal interconnect layers; performing a planarization process to remove the conductive material outside of the BTSV opening to form a back-side through-substrate-via (BTSV); and forming a conductive pad having a planar lower disposed onto the BTSV.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kao Min-Feng
• Yaung Dun-Nian
• Liu Jen-Cheng
• Huang Hsun-Ying

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title