Semiconductor package

Patent metadata

Field	Value
Publication number	US-2022044992-A1
Application number	US-202117509046-A
Country	US
Kind code	A1
Filing date	Oct 24, 2021
Priority date	Dec 18, 2018
Publication date	Feb 10, 2022
Grant date	—

Abstract

A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.

First claim

1 .- 23 . (canceled)

24 . A method of manufacturing a semiconductor package, the method comprising:
forming a first redistribution layer on a first carrier; forming a redistribution structure on the first carrier to cover the first redistribution layer, wherein the redistribution structure includes a plurality of insulation layers and a plurality of second redistribution layers respectively disposed between the plurality of insulation layers, each of the plurality of second redistribution layers having a connection via connected to an adjacent one of the first redistribution layer and the plurality of second redistribution layers; forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of second redistribution layers; mounting at least one semiconductor chip having a plurality of contact pads on the redistribution structure such that the plurality of contact pads are connected to the plurality of bonding pads, respectively; attaching a second carrier to an upper surface of the at least one semiconductor chip; removing the first carrier from a surface of the redistribution structure, in which the first redistribution layer is disposed; forming a base insulation layer on the surface of the redistribution structure to cover the first redistribution layer; and forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the first redistribution layer.

25 . The method of claim 24 , wherein the UBM pad has a thickness greater than that of each of the plurality of second redistribution layers.

26 . The method of claim 25 , wherein the UBM pad has a thickness of 10 μm or more

27 . The method of claim 24 ,
wherein each of the connection via and the bonding via has a tapered structure narrowed toward a first direction, and wherein the UBM via has a tapered structure narrowed toward a second direction opposed to the first direction.

28 . The method of claim 24 , further comprising:
after the forming the bonding pad, disposing at least one semiconductor chip on the base insulation layer to electrically connected to the bonding pad.

29 . The method of claim 24 , further comprising:
between the mounting the at least one semiconductor chip and the attaching the second carrier, forming a molding portion encapsulating the at least one semiconductor chip and grinding the molding portion to expose the upper surface of the at least one semiconductor chip.

30 . The method of claim 24 , wherein the mounting the at least one semiconductor chip comprises connecting the contact pads of the at least one semiconductor chip to the bonding pads, respectively, by using connection bumps

31 . The method of claim 30 , wherein the mounting the at least one semiconductor chip comprises forming an underfill resin to surround the connection bumps between the at least one semiconductor chip and the redistribution structure.

32 . The method of claim 24 , wherein each of the plurality of insulation layers comprises a photosensitive insulating material.

33 . The method of claim 32 , wherein the base insulation layers comprise a photosensitive insulating material.

34 . The method of claim 32 , wherein the base insulation layers comprise an insulating material different from that of each of the plurality of insulation layers.

35 . The method of claim 24 , wherein the UBM via has a width greater than that of the connection via.

36 . The method of claim 24 , wherein each of the plurality of redistribution layers is formed along with the connection via by a same process.

37 . The method of claim 24 , wherein the UBM pad is formed along with the UBM via by a same process.

38 . A method of manufacturing a semiconductor package, the method comprising:
forming a planar conductive pattern on a first carrier; forming a redistribution structure on the first carrier, wherein the redistribution structure includes a plurality of insulation layers, and a plurality of redistribution layers between the plurality of first insulation layers, each of the plurality of redistribution layers having a connection via connected to an adjacent one of planar conductive pattern and the plurality of redistribution layers; forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of redistribution layers disposing at least one semiconductor chip to electrically connect the plurality of bonding pads; forming a molding portion encapsulating the at least one semiconductor chip; grinding the molding portion to expose the upper surface of the at least one semiconductor chip; attaching a second carrier to the upper surface of the at least one semiconductor; removing the first carrier from a surface of the redistribution structure, in which the planar conductive pattern is disposed; forming a base insulation layer on the surface of the redistribution structure to cover the planar conductive pattern; and forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the planar conductive pattern.

39 . The method of claim 38 ,
wherein the UBM pad has a thickness greater than that of each of the plurality of redistribution layers, wherein the connection via has a tapered structure narrowed toward a first direction, and wherein the UBM via has a tapered structure narrowed toward a second direction opposite to the first direction.

40 . The method of claim 38 , wherein each of the plurality of insulation layers comprises a photosensitive insulating material and the base insulation layers comprise a photosensitive insulating material.

41 . A method of manufacturing a semiconductor package, the method comprising:
forming a planar conductive pattern on a first carrier; forming a redistribution structure on the first carrier, the redistribution structure including a plurality of insulation layers and a plurality of redistribution layers between the plurality of first insulation layers; forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of redistribution layers; disposing at least one semiconductor chip to electrically connect the plurality of bonding pads; attaching a second carrier to an upper surface of the at least one semiconductor chip; removing the first carrier from a surface of the redistribution structure in which the planar conductive pattern is disposed; forming a base insulation layer on the surface of the redistribution structure to cover the planar conductive pattern; and forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the planar conductive pattern.

42 . The method of claim 41 , wherein the forming the redistribution structure comprises:
forming a first insulation layer on the first carrier to cover the planar conductive pattern; forming a first hole in the first insulation layer, the first hole exposing a portion of the planar conductive pattern; forming a first redistribution layer on the first insulation layer, the first redistribution layer having a first connection via in the first hole connected to the exposed portion of the planar cond

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jung Ho
• Kim Jong Youn
• Bae Min Jun

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title