Printed circuit board

Patent metadata

Field	Value
Publication number	US-2022030713-A1
Application number	US-202117241357-A
Country	US
Kind code	A1
Filing date	Apr 27, 2021
Priority date	Jul 24, 2020
Publication date	Jan 27, 2022
Grant date	—

Abstract

A printed circuit board includes an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole penetrating through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, wherein the via comprises a first metal layer and a second metal layer disposed on the first metal layer, and an average size of grains in the first metal layer and an average size of grains in the second metal layer are different from each other.

First claim

What is claimed is:

1 . A printed circuit board, comprising:
an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole penetrating through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, wherein the via comprises a first metal layer and a second metal layer disposed on the first metal layer, and an average size of grains in the first metal layer and an average size of grains in the second metal layer are different from each other.

2 . The printed circuit board of claim 1 , wherein the average size of grains in the first metal layer is larger than the average size of grains in the second metal layer.

3 . The printed circuit board of claim 1 , wherein the second metal layer comprises a concave portion facing the metal pad on an interface between the first metal layer and the second metal layer, and
a third metal layer fills at least a portion of the concave portion.

4 . The printed circuit board of claim 1 , wherein the second metal layer comprises a first region and a second region, and
average sizes of grains in the first region and in the second region of the second metal layer are different from each other.

5 . The printed circuit board of claim 4 , wherein the first region of the second metal layer is disposed inside the via, and
the second region of the second metal layer is disposed outside the via and surrounds the first region.

6 . The printed circuit board of claim 5 , wherein the average size of grains in the first region of the second metal layer is larger than the average size of grains in the second region.

7 . The printed circuit board of claim 6 , wherein a third metal layer is disposed on the second metal layer, and an average size of grains in the third metal layer is smaller than the average size of grains in the first region of the second metal layer and larger than the average size of grains in the second region of the second metal layer.

8 . The printed circuit board of claim 1 , wherein the via further comprises a third metal layer covering at least a portion of a region exposed through the via hole of the metal pad and at least a portion of a wall surface of the via hole, and
the first metal layer is disposed on the third metal layer.

9 . The printed circuit board of claim 8 , wherein the second metal layer and the third metal layer extend onto a top surface of the insulating layer.

10 . The printed circuit board of claim 9 , wherein a thickness of the third metal layer is greater than a thickness of the second metal layer on the top surface of the insulating layer.

11 . The printed circuit board of claim 9 , wherein the via further comprises a fourth metal layer disposed on the top surface of the insulating layer, and
the first metal layer is disposed on the fourth metal layer on the top surface of the insulating layer.

12 . The printed circuit board of claim 1 , wherein the insulating layer, the metal pad, the via hole and the via respectively comprise a plurality of the insulating layers, a plurality of the metal pads, a plurality of the via holes and a plurality of the vias,
wherein: the plurality of the insulating layers are stacked, the plurality of the metal pads are disposed on one side of the plurality of the insulating layers, the plurality of the via holes penetrate a plurality of the insulating layers to expose at least a portion of a plurality of the metal pads, the plurality of the vias fill the plurality of the via holes, and at least two of the plurality of the vias overlap in a direction in which the insulating layers are stacked.

13 . A printed circuit board, comprising:
an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole penetrating through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, wherein the via comprises a first metal layer and a second metal layer comprising a first region and a second region and disposed on the first metal layer, and average sizes of grains in the first region and the second region of the second metal layer are different from each other.

14 . The printed circuit board of claim 13 , wherein the first region of the second metal layer is disposed inside the via, and
the second region of the second metal layer is disposed outside the via and surrounds the first region.

15 . The printed circuit board of claim 14 , wherein an average size of grains in the first region of the second metal layer is larger than an average size of grains in the second region.

16 . The printed circuit board of claim 15 , wherein an average size of grains in the third metal layer is smaller than the average size of grains in the first region of the second metal layer and larger than the average size of grains in the second region.

17 . The printed circuit board of claim 1 , wherein the second metal layer does not extend onto a top surface of the insulating layer.

18 . The printed circuit board of claim 1 , wherein a third metal layer is directly disposed the first metal layer disposed on the top surface of the insulating layer.

19 . A printed circuit board, comprising:
an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole penetrating through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, wherein the via comprises a second metal layer comprising a first region and a second region and a third metal layer, and average sizes of grains in the first region and in the second region of the second metal layer are different from each other.

20 . The printed circuit board of claim 19 , wherein an average size of grains in the first region of the second metal layer is larger than an average size of grains in the second region of the second metal layer.

Assignees

• Samsung Electro Mech

Inventors

• Mun Seong Jae
• Choi Jong Chan

Classifications

• H05K2201/0269

  Non-uniform distribution or concentration of particles · CPC title

• H05K2203/0723

  Electroplating, e.g. finish plating · CPC title

• H05K2201/0266

  Size distribution · CPC title

• H05K3/421

  Blind plated via connections (H05K3/422, H05K3/423 and H05K3/425 take precedence) · CPC title

• H05K3/423 Primary

  characterised by electroplating method · CPC title