Phase-locked loop circuit and digital-to-time convertor error cancelation method thereof

Patent metadata

Field	Value
Publication number	US-2021359687-A1
Application number	US-202117242395-A
Country	US
Kind code	A1
Filing date	Apr 28, 2021
Priority date	May 14, 2020
Publication date	Nov 18, 2021
Grant date	—

Abstract

A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.

First claim

What is claimed is:

1 . A phase-locked loop (PLL) circuit, comprising:
a first DTC, for receiving a first delay control signal to dither a reference signal or a feedback signal; a first selection circuit, coupled to the first DTC, for receiving the reference signal and the feedback signal, and according to a selection signal, transmitting the reference signal or the feedback signal to the first DTC; and a second selection circuit, coupled to the first DTC and the first selection circuit, according to the selection signal, determining output paths of an output reference signal and an output feedback signal.

2 . The PLL circuit of claim 1 , wherein the first selection circuit comprises a first multiplexer and a second multiplexer, and the second selection circuit comprises a third multiplexer and a fourth multiplexer, or wherein the first selection circuit comprises a first switch and a second switch, and the second selection circuit comprises a third switch and a fourth switch.

3 . The PLL circuit of claim 1 , wherein in a first cycle, the selection signal is a first value, the first selection circuit transmits the reference signal to the first DTC; and in a second cycle, the selection signal is a second value, the first selection circuit transmits the feedback signal to the first DTC.

4 . The PLL circuit of claim 3 , wherein in the first cycle, the second selection circuit outputs the output reference signal based on its first input from the first DTC and outputs the output feedback signal based on its second input from the first selection circuit; and in the second cycle, the second selection circuit outputs the output feedback signal based on its first input from the first DTC and outputs the output reference signal based on its second input from the first selection circuit.

5 . The PLL circuit of claim 3 , wherein the first delay control signal has a same setting during the first cycle and the second cycle.

6 . The PLL circuit of claim 1 , further comprising:
a second DTC, coupled to the first selection circuit and the second selection circuit, for receiving a second delay control signal to dither the reference signal or the feedback signal, wherein according to the selection signal, the first selection circuit transmits the reference signal or the feedback signal to the second DTC, and wherein according to the reference signal, the second selection circuit determines to output the output reference signal based on its first input from the first DTC and output the output feedback signal based on its second input from the second DTC, or to output the output feedback signal based on its first input from the first DTC and output the output reference signal based on its second input from the second DTC according to the selection signal.

7 . The PLL circuit of claim 6 , wherein the second delay control signal has a same setting during the first cycle and the second cycle.

8 . The PLL circuit of claim 1 , wherein the second selection circuit transmits the output reference signal and the output feedback signal to a phase-frequency detector (PFD) or a time-to-digital convertor (TDC).

9 . The PLL circuit of claim 1 , wherein a PFD is configured between the first TDC and the second selection circuit, or is configured in the front of the first selection circuit.

10 . A digital-to-time convertor (DTC) error cancelation method, applied to a phase-locked loop (PLL) circuit, comprising:
receiving, by a first selection circuit of the PLL circuit, a reference signal and a feedback signal; transmitting, by the first selection circuit, the reference signal or the feedback signal to a first DTC of the PLL circuit according to a selection signal; dithering, by the first DTC, the reference signal or the feedback signal according to a first delay control signal; and determining, by a second selection circuit of the PLL circuit, output paths of an output reference signal and an output feedback signal according to the selection signal.

11 . The DTC error cancelation method of claim 10 , wherein the first selection circuit comprises a first multiplexer and a second multiplexer, and the second selection circuit comprises a third multiplexer and a fourth multiplexer, or wherein the first selection circuit comprises a first switch and a second switch, and the second selection circuit comprises a third switch and a fourth switch.

12 . The DTC error cancelation method of claim 10 , wherein in a first cycle, the selection signal is a first value, and the method further comprises:
transmitting, by the first selection circuit, the reference signal to the first DTC.

13 . The DTC error cancelation method of claim 12 , wherein in a second cycle, the selection signal is a second value, and the method further comprises:
transmitting, by the first selection circuit, the feedback signal to the first DTC.

14 . The DTC error cancelation method of claim 13 , wherein in the first cycle, the method further comprises:
outputting, by the second selection circuit, the output reference signal based on its first input from the first DTC and the output feedback signal based on its second input from the first selection circuit.

15 . The DTC error cancelation method of claim 13 , wherein in the second cycle, the method further comprises:
outputting, by the second selection circuit, the output feedback signal based on its first input from the first DTC and the output reference signal based on its second input from the second DTC.

16 . The DTC error cancelation method of claim 13 , wherein the first delay control signal has a same setting during the first cycle and the second cycle.

17 . The DTC error cancelation method of claim 10 , further comprising:
receiving, by a second DTC of the PLL circuit, a second delay control signal to dither the reference signal or the feedback signal; transmitting, by the first selection circuit, the reference signal or the feedback signal to the second DTC according to the selection signal; and determining, by the second selection circuit, to output the output reference signal based on its first input from the first DTC and output the output feedback signal based on its second input from the second DTC, or to output the output feedback signal based on its first input from the first DTC and output the output reference signal based on its second input from the second DTC according to the selection signal.

18 . The DTC error cancelation method of claim 17 , wherein the second delay control signal has a same setting during the first cycle and the second cycle.

19 . The DTC error cancelation method of claim 10 , further comprising:
transmitting, by the second selection circuit, the output reference signal and the output feedback signal to a phase-frequency detector (PFD) or a time-to-digital convertor (TDC).

20 . The DTC error cancelation method of claim 10 , wherein a PFD is configured between the first TDC and the second selection circuit, or is configured in the front of the first selection circuit.

Assignees

• Mediatek Inc

Inventors

• Chiu Wei-Hao
• Lin Ang-Sheng
• Chueh Tzu-Chan

Classifications

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/081 Primary

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/08 Primary

  Details of the phase-locked loop · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title