Analog fractional-n phase-locked loop

Patent metadata

Field	Value
Publication number	US-2017366376-A1
Application number	US-201715629509-A
Country	US
Kind code	A1
Filing date	Jun 21, 2017
Priority date	Jun 21, 2016
Publication date	Dec 21, 2017
Grant date	—

Abstract

An analog fractional-N phase-locked loop includes an oscillator loop having a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor. Output of the fractional feedback divider is fed back to the feedback input. A compensation circuit is coupled to, and configured to apply a time delay to, the reference input or the feedback input, to compensate for delay introduced by the fractional feedback divider. The compensation circuit may be a digital-to-time converter configured to convert a digital delay signal into the time delay. The digital-to-time converter may be coupled to the reference input to delay signals to match feedback delay introduced by the fractional feedback divider, or to the feedback input to subtract the time delay to cancel feedback delay introduced by the fractional feedback divider.

First claim

What is claimed is:

1 . An analog fractional-N phase-locked loop, comprising:
an oscillator loop having: a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor, wherein output of the fractional feedback divider is fed back to the feedback input; and a compensation circuit coupled to one of the reference input and the feedback input, the compensation circuit configured to apply a time delay to the one of the reference input and the feedback input to compensate for delay introduced by the fractional feedback divider.

2 . The analog fractional-N phase-locked loop of claim 1 wherein the compensation circuit is a digital-to-time converter configured to convert a digital delay signal into the time delay.

3 . The analog fractional-N phase-locked loop of claim 2 , wherein the digital-to-time converter is coupled to the reference input and is configured to delay signals on the reference input by the time delay to match feedback delay introduced by the fractional feedback divider.

4 . The analog fractional-N phase-locked loop of claim 2 , wherein the digital-to-time converter is coupled to the feedback input and subtracts the time delay from signals on the feedback input to cancel feedback delay introduced by the fractional feedback divider.

5 . The analog fractional-N phase-locked loop of claim 2 , wherein:
the oscillator loop further comprises a loop filter configured to filter out frequency noise components; and the digital delay signal to control the digital-to-time converter is derived based at least in part on an output of the loop filter.

6 . The analog fractional-N phase-locked loop of claim 5 , wherein the analog fractional-N phase-locked loop further comprises:
an analog integrator configured to integrate the output of the loop filter to generate an analog delay signal; and an analog-to-digital converter configured to digitize the analog delay signal thereby to provide the digital delay signal to control the digital-to-time converter.

7 . The analog fractional-N phase-locked loop of claim 6 wherein:
a sign signal, representative of direction of phase mismatch, is derived from the fractional feedback divider;
the oscillator loop further comprises a switch configured to, based on the sign signal, select a path from between two paths through the loop filter; and
the analog integrator is connected to outputs of both of the two paths through the loop filter.

8 . The analog fractional-N phase-locked loop of claim 5 , wherein:
an error signal, representative of delay introduced by the fractional feedback divider, is output by the fractional feedback divider; the loop filter is a sample-and-hold low-pass filter including a sample-and-hold switch; and the analog fractional-N phase-locked loop further comprises: a comparator connected across the sample-and-hold switch to derive a sign signal, and a correlator configured to multiply the sign signal by the error signal to provide the control signal.

9 . The analog fractional-N phase-locked loop of claim 1 , wherein:
the divisor includes a fractional value; and the fractional feedback divider comprises a feedback divider configured to divide signals on the loop output by a respective integral value at each respective clock cycle, and a sigma-delta modulator configured to generate the respective integral value at each respective clock cycle based on the divisor.

10 . A wireless transceiver including the analog fractional-N phase-locked loop of claim 1 .

11 . A method of operating an analog fractional-N phase-locked loop, including an oscillator loop having a reference input, a feedback input, and a loop output, and having a fractional feedback divider configured to divide signals on the loop output by a divisor, wherein output of the fractional feedback divider is fed back to the feedback input, the method comprising:
measuring delay introduced by the fractional feedback divider; and compensating for the feedback delay introduced by the fractional feedback divider by applying a time delay to the one of the reference input and the feedback input.

12 . The method of claim 11 , wherein:
the measuring comprises deriving a digital delay signal representative of the delay introduced by the fractional feedback divider; and the compensating comprises converting the digital delay signal to the time delay.

13 . The method of claim 12 , wherein the compensating is performed by a digital-to-time converter coupled to the reference input, and comprises delaying signals on the reference input to match the feedback delay introduced by the fractional feedback divider.

14 . The method of claim 12 , wherein the compensating is performed by a digital-to-time converter coupled to the feedback input, and comprises subtracting delay from signals on the feedback input to cancel the feedback delay introduced by the fractional feedback divider.

15 . The method of claim 12 , wherein the deriving a digital delay signal is performed based at least in part on an output of a loop filter in the oscillator loop.

16 . The method of claim 15 , wherein the deriving a digital value comprises:
performing analog integration at the output of the loop filter; and digitizing a result of the analog integration to provide the digital delay signal.

17 . The method of claim 16 further comprising:
deriving a sign signal, representative of direction of phase mismatch between the reference input and the loop output, from the fractional feedback divider; and
selecting a path, based on the sign signal, from between two paths through the loop filter; wherein:
the analog integration is performed on outputs of both of the two paths through the loop filter.

18 . The method of claim 15 , wherein the loop filter is a sample-and-hold low-pass filter including a sample-and-hold switch, the method further comprising:
deriving a sign signal by comparing voltages on both sides of the sample-and-hold switch; deriving an error signal indicative of a rounding error from the fractional feedback divider; and multiplying the sign signal by the error signal to provide the digital value.

19 . A compensation circuit for an analog fractional-N phase-locked loop including an oscillator loop having a reference input, a feedback input, a loop filter and a loop output, and having a fractional feedback divider in a feedback position between the loop output and the feedback input, the compensation circuit comprising:
circuitry that is configured to measure delay introduced by the fractional feedback divider; and circuitry that is configured to compensate for the feedback delay introduced by the fractional feedback divider by applying a time delay to the one of the reference input and the feedback input.

20 . The compensation circuit of claim 19 wherein the circuitry that compensates comprises a digital-to-time converter configured to convert a digital delay signal into the time delay.

21 . The compensation circuit of claim 20 wherein:
the circuitry that measures comprises an analog integrator at an output of the loop filter; and
the analog integrator is configured to integrate the output of the loop filter to generate an analog delay signal.

22 . The compensation circuit of claim 20 wherein:
the loop filter includes a sample-and-hold low-pass filter having a sample-and-hold switch; and
the circuitry that measures compr

Assignees

• Marvell World Trade Ltd

Inventors

• Wang Haisong
• Gao Xiang
• Burg Olivier
• Tu Cao-Thong

Classifications

• H04L27/0014

  Carrier regulation (of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657) · CPC title

• H03L7/081

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/1806 Primary

  the frequency divider comprising a phase accumulator generating the frequency divided signal · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title