Adaptively reconfigurable time-to-digital converter for digital phase-locked loops

Patent metadata

Field	Value
Publication number	US-9979405-B1
Application number	US-201715429481-A
Country	US
Kind code	B1
Filing date	Feb 10, 2017
Priority date	Feb 10, 2017
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A digital PLL is disclosed. In one embodiment, the digital PLL includes a TDC coupled to receive a reference clock signal and feedback signal. The TDC includes a chain of serially-coupled delay elements. An oscillator in the PLL is configured to generate a periodic output signal. A divider is coupled to receive the periodic output signal and generate the feedback signal provided to the TDC. The digital PLL also includes a control circuit. During a phase-locking procedure, each of the serially-coupled delay elements is enabled for fast phase capture. However, once phase-lock has been detected by observing TDC output code, the control circuit is adaptively configured to disable all but a subset of the delay elements for saving power.

First claim

What is claimed is:

1. A phase-locked loop (PLL) circuit comprising:
a time-to-digital converter (TDC) circuit configured to receive a reference clock signal on a first input and a feedback signal on a second input, the TDC including at least a first plurality of serially-coupled delay elements;
an oscillator configured to generate a periodic output signal;
a divider circuit configured to generate the feedback signal based on a PLL output signal provided by the oscillator; and
a control circuit configured to enable each of the first plurality of serially-coupled delay elements during a phase-locking procedure, and further configured to, responsive to the PLL achieving phase-lock, disable all but a subset of the first plurality of serially-coupled delay elements.

2. The PLL circuit as recited in claim 1 , further comprising a plurality of comparator circuits each coupled to a corresponding ones of first plurality of serially-coupled delay elements, wherein each of the each of the comparator circuits is configured to compare a received value of the reference clock signal to a received value of the feedback signal.

3. The PLL circuit as recited in claim 2 , further comprising a second plurality of serially-coupled delay elements coupled to receive the feedback clock signal, each of the second plurality of serially-coupled delay elements having an output coupled to a corresponding one of the plurality of comparator circuits, and wherein the control circuit is further configured to:
enable each of the second plurality of serially-coupled delay elements and each of the plurality of comparator circuits during the phase-locking procedure; and
disable all but a subset of the second plurality of serially-coupled delay elements disable all but a subset of the comparator circuits responsive to the PLL achieving phase-lock.

4. The PLL circuit as recited in claim 3 , wherein the control circuit is configured to disable subsets of the first and second pluralities of serially-coupled delay elements and the plurality of comparator circuits by removing power from the first and second pluralities of serially-coupled delay elements and the plurality of comparator circuits.

5. The PLL circuit as recited in claim 3 , wherein a first one of the first plurality of serially-coupled delay elements is coupled to receive the reference clock signal, and wherein a first one of the second plurality of serially-coupled delay elements is coupled to receive the feedback signal.

6. The PLL circuit as recited in claim 2 , further comprising a thermometer-to-binary code circuit coupled to receive a respective output signal from each of the plurality of comparator circuits, wherein the thermometer-to-binary code circuit is configured to generate a binary code based on the respective output signals received from each of the plurality of comparator circuits.

7. The PLL circuit as recited in claim 6 , further comprising a lead/lag circuit configured to determine if the reference clock is leading or lagging the feedback signal, and a sign bit circuit coupled to receive a lead/lag indication from the lead/lag circuit, wherein the sign bit circuit is configured to output a sign bit having a value depending on whether the binary code represents a positive or negative value.

8. The PLL circuit as recited in claim 1 , further comprising a digital low low-pass filter coupled to receive an output signal from the TDC further coupled to provide an output signal to the oscillator.

9. The PLL circuit as recited in claim 8 , wherein the oscillator is a digitally controlled oscillator, and wherein the output signal from the TDC is a digital code, wherein a frequency of the periodic output signal corresponds to the digital code.

10. The PLL circuit as recited in claim 8 , wherein the digital low-pass filter is configured to generate a voltage signal, wherein the oscillator is a voltage-controlled oscillator, and wherein a frequency of the periodic output signal is dependent on the voltage signal.

11. A method comprising:
a divider circuit generating a feedback signal by dividing a periodic output signal received from an oscillator;
performing a locking procedure in a digital phase-locked loop (PLL) circuit, wherein performing the locking procedure comprises providing, to a time-to-digital converter (TDC) circuit, a reference clock signal on a first input and a feedback signal on a second input, the TDC including a plurality of serially-coupled delay elements, wherein performing the locking procedure includes a control circuit enabling each of the plurality of serially-coupled delay elements during; and
responsive to achieving a phase-lock, a control circuit disabling all but a subset of the plurality of serially-coupled delay elements.

12. The method as recited in claim 11 , further comprising:
each of a plurality of comparators receiving, during the locking procedure, the reference clock signal and an output signal from a correspondingly coupled one of the plurality of serially-coupled delay elements;
each of the plurality of comparators comparing, a level of the feedback signal to a level of the output signal received from its correspondingly coupled one of the plurality of delay elements.

13. The method as recited in claim 12 , wherein disabling all but the subset of the plurality of serially-coupled delay elements comprises powering down all but the subset of the plurality of serially-coupled delay elements, and wherein the method further comprises disabling all but a subset of the plurality of comparators coupled to particular ones of the subset of the plurality of serially-coupled delay elements.

14. The method as recited in claim 12 , further comprising:
during the locking procedure, providing output signals from each of the plurality of comparators to a thermometer-to-binary code circuit; and
generating a binary code based on the respective output signals received from each of the plurality of comparators.

15. The method as recited in claim 11 , further comprising:
providing an output from the TDC to a digital low-pass filter;
providing one or more output signals from the digital low-pass filter to the oscillator; and
generating the periodic output signal at a frequency dependent on the one or more output signals.

16. A phase-locked loop (PLL) comprising:
a time-to-digital converter (TDC) circuit configured to receive a reference clock signal on a first input and a feedback signal on a second input, wherein the TDC circuit includes a first plurality of serially-coupled delay elements, a second plurality of serially-coupled delay elements, and a plurality of comparator circuits each coupled to corresponding ones of first and second pluralities of serially-coupled delay elements;
a low-pass filter circuit coupled to receive an output from the TDC circuit;
a voltage controlled oscillator (VCO) coupled to receive an output from the low-pass filter circuit;
a divider circuit configured to generate the feedback signal based on a PLL output signal provided by the VCO; and
a control circuit, wherein the control circuit is configured to, prior to the TDC circuit indicating a phase lock, enable each delay element of the first and second pluralities of delay elements, and further configured to, responsive to the TDC circuit indicating a phase lock:
disable a subset of the delay elements of the first and second pluralities of delay elements; and
disable a subset of the plurality of comparator circuits.

17. The PLL as recited in claim 16 , wherein the control circuit is configured to disable subsets of the first a

Assignees

• Apple Inc

Inventors

• Deng Wei
• Fischette Jr Dennis M
• Chiang Meei-Ling
• Maltabas Samed

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/095 Primary

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/081 Primary

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title