Spur reduction in phase locked loops using reference clock dithering

Patent metadata

Field	Value
Publication number	US-9628262-B1
Application number	US-201615213574-A
Country	US
Kind code	B1
Filing date	Jul 19, 2016
Priority date	Jul 19, 2016
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

An embodiment of the present disclosure provides a phase locked loop. A controllable oscillator generates a radio frequency (RF) signal. A divider is configured to produce a divided RF signal by dividing the RF signal by a division factor. A phase detection circuit is configured to receive a dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator. A dithering module is configured produce the dithered reference signal and the division factor, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and a target frequency of the RF signal.

First claim

What is claimed is:

1. A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:
a controllable oscillator for generating a radio frequency (RF) signal having a target frequency;
a divider coupled to receive the RF signal, the divider configured to produce a divided RF signal by dividing the RF signal by a division factor;
a phase detection circuit configured to receive a dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator; and
a dithering module configured to receive a reference signal having a fixed frequency FREF, the dithering module operable to produce the dithered reference signal and the division factor, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and the target frequency of the RF signal.

2. The PLL of claim 1 , in which the dithering module includes:
selection circuitry configured to randomly select a count value C from at least two defined dither values; and
counting circuit operable to count each period of the reference signal and produce one period of the dithered reference signal every C periods of the reference signal.

3. The PLL of claim 2 , further including a pseudo random number (PRN) generator, in which a bit signal of the PRN generator is coupled to control the selection circuitry.

4. The PLL of claim 2 , in which the selection circuitry switches at an average time rate of less than one microsecond.

5. The PLL of claim 2 , further including:
storage for holding at least two division factor values; and
selection logic configured to select a division factor corresponding to each selected count value.

6. The PLL of claim 1 , in which the divider includes a counter configured to divide the RF signal by counting a number of periods of the RF signal defined by the division factor.

7. The PLL of claim 1 , in which the dithering module includes:
at least two dividers configured to divide the reference signal to form at least two divided reference signals; and
selection circuitry configured to randomly select any of the at least two divided reference signals to form the dithered reference signal.

8. The PLL of claim 7 , further including a pseudo random number (PRN) generator, in which a bit signal of the PRN generator is coupled to control the selection circuitry.

9. The PLL of claim 7 , in which the selection circuitry switches at an average time rate of less than one microsecond.

10. The PLL of claim 7 , further including:
storage for holding at least two division factor values; and
selection logic configured to select a division factor corresponding to each selected divided reference signal.

11. The digital system of claim 1 being a communication device, further including a transmitter having modulation logic configured to modulate the RF signal.

12. The communication device of claim 11 , further including an RF receiver coupled to operate using the RF signal.

13. A method for operating a phase locked loop (PLL), the method comprising:
generating a reference clock having a frequency FREF;
generating an adjustable radio frequency (RF) signal having a target frequency;
dithering the reference clock to generate a dithered reference clock having a randomly changing frequency selected from a plurality of dither frequencies;
selecting a division factor to match a ratio between each selected dither frequency and the target frequency of the RF signal;
dividing the RF signal by the selected division factor to produce a divided RF signal;
detecting a phase error between the dithered reference dock and the divided RF signal; and
adjusting the adjustable RF signal to minimize the phase error.

14. The method of claim 13 , in which dithering the reference clock is performed by dividing the frequency of the reference clock each of two or more values in a random sequence.

15. The method of claim 14 , in which the random sequence is a pseudo random sequence.

16. The method of claim 13 , in which dithering the reference clock switches frequency of the dithered reference clock at an average time rate of less than one microsecond.

17. An integrated circuit comprising:
a phase locked loop (PLL), in which the PLL includes:
a controllable oscillator for generating a radio frequency (RF) signal having a target frequency;
a control loop controllably coupled to the controllable oscillator; and
a dithering module having a dithered reference signal output and a division factor output coupled to the control loop, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and the target frequency of the RF signal.

18. The integrated circuit of claim 17 , in which the control loop includes:
a divider coupled to receive the RF signal, the divider configured to produce a divided RF signal by dividing the RF signal by the division factor; and
a phase detection circuit configured to receive the dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator.

19. The integrated circuit of claim 17 , in which the dithering module includes:
selection circuitry configured to randomly select a count value C from at least two defined dither values; and
counting circuit operable to count each period of the reference signal and produce one period of the dithered reference signal every C periods of the reference signal.

20. The PLL of claim 19 , further including a pseudo random number (PRN) generator, in which a bit signal of the PRN generator is coupled to control the selection circuitry.

Assignees

• Texas Instruments Inc

Inventors

• Moe Marius

Classifications

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04B15/02 Primary

  Reducing interference from electric apparatus by means located at or near the interfering apparatus · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03L7/183

  a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)} · CPC title

• H04L7/06

  the synchronisation signals differing from the information signals in amplitude, polarity or frequency {or length} · CPC title