Method for measuring chips bonding strength and chips bonding auxiliary structure

Patent metadata

Field	Value
Publication number	US-2021358818-A1
Application number	US-202016906330-A
Country	US
Kind code	A1
Filing date	Jun 19, 2020
Priority date	May 12, 2020
Publication date	Nov 18, 2021
Grant date	—

Abstract

A method for measuring chips bonding strength includes steps as follows: An auxiliary pattern is formed on a first surface of a first chip. A second surface of a second chip is bonded to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, dimensions of the at least one gap space and the auxiliary pattern are measure respectively; and the bonding strength between the first chip and the second chip is estimated according to the dimensions.

First claim

What is claimed is:

1 . A method for measuring chips bonding strength, comprising:
forming an auxiliary pattern on a first surface of a first chip; bonding a second surface of a second chip to the first surface to form at least one gap space surrounding the auxiliary pattern; measuring dimensions of the at least one gap space and the auxiliary pattern respectively; and estimating the bonding strength between the first chip and the second chip according to the dimensions.

2 . The method according to claim 1 , wherein the step of forming the auxiliary pattern comprises:
performing a deposition process to form a deposition layer on the first surface, wherein a boundary surface is formed between the deposition layer and the first surface; and performing an etching process to remove a portion of the deposition layer, to form a patterned layer.

3 . The method according to claim 1 , wherein the step of forming the auxiliary pattern comprises performing a focused ion beam (FIB) deposition process on the first surface to form a deposition patterned layer.

4 . The method according to claim 1 , wherein the auxiliary pattern comprises a plurality of convex pillars; the at least one gap space comprises a plurality of gap spaces; and each of the plurality of gap spaces correspondingly surrounds single one of the plurality of convex pillars.

5 . The method according to claim 4 , wherein the estimating the bonding strength is estimated according to demotions of the plurality of gap spaces and the modulus of elasticities of the first chip and the second chip.

6 . The method according to claim 5 , wherein the step of estimating the bonding strength comprises:
obtaining a thickness t 1 of the carrier substrate, a modulus of elasticity E 1 of the carrier substrate, a thickness t 2 of the device substrate, a modulus of elasticity E 2 of the device substrate, an average height h of the plurality of convex pillars, and an average radius R of the plurality of gap spaces; and calculating the bonding strength y using a Formula (I) as follows:

R
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Formula
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I
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7 . The method according to claim 1 , wherein the auxiliary pattern comprises a plurality of convex pillars; the at least one gap space comprises a plurality of gap spaces; and each of the plurality of gap spaces correspondingly surrounds several ones of the plurality of convex pillars.

8 . The method according to claim 1 , wherein the step of measuring the dimensions of the at least one gap space and the auxiliary pattern comprises an ultrasonic measurement or an optical measurement.

9 . The method according to claim 8 , wherein the ultrasonic measurement comprises using of a confocal scanning acoustic microscopy (CSAM).

10 . The method according to claim 8 , wherein the optical measurement comprises using of a laser triangulation technique.

11 . The method according to claim 6 , wherein each of the plurality of convex pillars has a bottom area substantially ranging from 0.002 square millimeters (mm 2 ) to 0.03 mm 2 ; the average height h ranges from 50 micrometer (μm) to 100 μm; and each of the plurality of gap spaces has a projected area ranging from 500 mm 2 to 1000 mm 2 .

12 . The method according to claim 1 , further comprising a thermal annealing process performed prior to the step of measuring the dimensions of the at least one gap space and the auxiliary pattern.

13 . A chips bonding auxiliary structure, comprising:
a first chip having a first surface; an auxiliary pattern form on the first surface; and a second chip having a second surface bonding to the first surface to form at least one gap space surrounding the auxiliary pattern.

14 . The chips bonding auxiliary structure according to claim 13 , wherein the auxiliary pattern comprises a plurality of convex pillars; the at least one gap space comprises a plurality of gap spaces;

Assignees

• United Microelectronics Corp

Inventors

• Zhang Sheng
• Pang Chien-Kee
• Zhao Xin

Classifications

• H10P74/27

  Structural arrangements therefor · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G01N19/04 Primary

  Measuring adhesive force between materials, e.g. of sealing tape, of coating · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title