Thin film resistor (tfr) formed in an integrated circuit device using an oxide cap layer as a tfr etch hardmask

Patent metadata

Field	Value
Publication number	US-2021273037-A1
Application number	US-202017071584-A
Country	US
Kind code	A1
Filing date	Oct 15, 2020
Priority date	Mar 2, 2020
Publication date	Sep 2, 2021
Grant date	—

Abstract

A process is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. An oxide cap is formed over the TFR film, which acts as a hardmask during a TFR etch of the TFR film to define a TFR element, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer. TFR edge spacers may be formed over lateral edges of the TFR element to insulate such TFR element edges. TFR contact openings are etched in the oxide cap over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element.

First claim

1 . A method of forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device, the method comprising:
forming an integrated circuit (IC) structure including a plurality of IC elements and a plurality of conductive IC element contacts connected to the plurality of IC elements; forming a TFR film layer over the IC structure; annealing the TFR film layer; forming a TFR oxide cap layer over the annealed TFR film layer; forming and patterning a first photomask over the TFR oxide cap layer; performing an oxide cap etch process to remove selected portions of the TFR oxide cap layer to define a TFR oxide cap, wherein the first etch process stops at the annealed TFR film layer; removing the first photomask; after removing the first photomask, performing a TFR etch process, using the TFR oxide cap as a hardmask, to remove selected portions of the annealed TFR film layer to define a TFR element; performing a TFR contact opening etch process to form at least one TFR contact opening in the TFR oxide cap, thereby exposing at least one surface area of the TFR element; and forming a metal interconnect layer over the IC structure and including (a) at least one metal interconnect element coupled to at least one of the plurality of conductive IC element contacts and (b) at least one metal interconnect extending into the at least one TFR contact opening to contact the underlying TFR element.

2 . The method of claim 1 , further comprising:
forming a first etch stop layer over the IC structure prior to forming the TFR film layer; after the TFR etch process and prior to the TFR contact opening etch process, performing an etch stop layer etch process to remove selected portions of the first etch stop layer.

3 . The method of claim 1 , wherein the oxide cap etch process rounds upper corners of the TFR oxide cap.

4 . The method of claim 1 , wherein the integrated circuit structure includes a memory cell or transistor structure including at least one conductive IC element contact connected to at least one of a source region, a drain region, and a gate region of the memory cell or transistor structure.

5 . The method of claim 1 , wherein the TFR film layer comprises silicon carbide chromium (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta 2 Si), or titanium nitride (TiN).

6 . The method of claim 1 , wherein the metal interconnect layer comprises aluminum.

7 . The method of claim 1 , wherein the TFR anneal is performed prior to depositing the metal interconnect layer.

8 . The method of claim 1 , wherein the TFR anneal comprises an anneal at a temperature of at least 500° C.

9 . The method of claim 1 , wherein the TFR anneal comprises an anneal at a temperature of 515° C.±10° C. for a duration of 15-60 minutes (e.g., 30 min).

10 . The method of claim 1 , wherein the TFR contact etch process comprises a wet etch.

11 . The method of claim 1 , wherein forming the metal interconnect layer includes forming a particular metal interconnect element defining a conductive connection between the TFR element and at least one of the plurality of conductive IC element contacts.

12 . A method of forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device, the method comprising:
forming an integrated circuit (IC) structure including a plurality of IC elements and a plurality of conductive IC element contacts connected to the plurality of IC elements; forming a TFR film layer over the IC structure; annealing the TFR film layer; forming a TFR oxide cap layer over the annealed TFR film layer; forming and patterning a first photomask over the TFR oxide cap layer; performing an oxide cap etch process to remove selected portions of the TFR oxide cap layer to define a TFR oxide cap, wherein the first etch process stops at the annealed TFR film layer; removing the first photomask; after removing the first photomask, performing a TFR etch process, using the TFR oxide cap as a hardmask, to remove selected portions of the annealed TFR film layer to define a TFR element; forming a spacer layer over the TFR oxide cap; performing a spacer etch process to remove first portions of the spacer layer but leaving second portions of the spacer layer that define TFR edge spacers at lateral edges of the TFR element; performing a TFR contact opening etch process to form at least one TFR contact opening in the TFR oxide cap, thereby exposing at least one surface area of the TFR element; and forming a metal interconnect layer over the IC structure and including (a) at least one metal interconnect element coupled to at least one of the plurality of conductive IC element contacts and (b) at least one metal interconnect extending into the at least one TFR contact opening to contact the underlying TFR element.

13 . The method of claim 12 , wherein the spacer layer comprises an oxide spacer layer.

14 . The method of claim 12 , wherein the spacer layer comprises a nitride spacer layer.

15 . The method of claim 12 , further comprising:
forming a first etch stop layer over the IC structure prior to forming the TFR film layer; and after the spacer etch process and prior to the TFR contact opening etch process, performing an etch stop layer etch process to remove selected portions of the first etch stop layer.

16 . The method of claim 12 , further comprising:
forming a first etch stop layer over the IC structure prior to forming the TFR film layer; and after the oxide cap etch process and prior to forming the spacer layer, performing an etch stop layer etch process to remove selected portions of the first etch stop layer.

17 . The method of claim 12 , wherein the oxide cap etch process rounds upper corners of the TFR oxide cap.

18 . The method of claim 12 , wherein each TFR edge oxide spacer has a rounded, non-vertical outer sidewall that reduces the likelihood of electrical shorts associated with the TFR element.

19 . The method of claim 12 , wherein the integrated circuit structure includes a memory cell or transistor structure including at least one conductive IC element contact connected to at least one of a source region, a drain region, and a gate region of the memory cell or transistor structure.

20 . The method of claim 12 , wherein the TFR film layer comprises silicon carbide chromium (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta 2 Si), or titanium nitride (TiN).

21 . The method of claim 12 , wherein the metal interconnect layer comprises aluminum.

22 . The method of claim 12 , wherein the TFR anneal is performed prior to depositing the metal interconnect layer.

Assignees

• Microchip Tech Inc

Inventors

• Fest Paul
• Williams Jacob
• Kaufman Josh
• Dix Greg

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10D1/47 Primary

  Resistors having no potential barriers · CPC title

• H10D1/474 Primary

  comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides · CPC title

• H01L28/20 Primary

  Electricity · mapped topic