Thin film resistor (TFR) formed in an integrated circuit device using wet etching of a dielectric cap
US-11990257-B2 · May 21, 2024 · US
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Fest Paul patents
Fest Paul is listed as an inventor on 35 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Fest Paul |
| Total patents | 35 |
| First publication | May 19, 2015 |
| Latest publication | May 21, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Thin film resistor (TFR) formed in an integrated circuit device using TFR cap layer(s) as an etch stop and/or hardmask
US-11508500-B2 · Nov 22, 2022 · US
Thin film resistor (TFR) formed in an integrated circuit device using an oxide cap layer as a TFR etch hardmask
US-11495657-B2 · Nov 8, 2022 · US
Thin film resistor (tfr) formed in an integrated circuit device using wet etching of a dielectric cap
US-2021272726-A1 · Sep 2, 2021 · US
Thin film resistor (tfr) formed in an integrated circuit device using tfr cap layer(s) as an etch stop and/or hardmask
US-2021272725-A1 · Sep 2, 2021 · US
Thin film resistor (tfr) formed in an integrated circuit device using an oxide cap layer as a tfr etch hardmask
US-2021273037-A1 · Sep 2, 2021 · US
Forming a thin film resistor (TFR) in an integrated circuit device
US-11088024-B2 · Aug 10, 2021 · US
Forming a thin film resistor (tfr) in an integrated circuit device
US-2020328115-A1 · Oct 15, 2020 · US
Systems and methods for forming a thin film resistor integrated in an integrated circuit device
US-10763324-B2 · Sep 1, 2020 · US
Spacer enabled poly gate
US-10290503-B2 · May 14, 2019 · US
Recent patents
Latest publications not already listed above.
Systems And Methods For Forming A Thin Film Resistor Integrated In An Integrated Circuit Device
US-2019035878-A1 · Jan 31, 2019 · US
Resistive Memory Cell With Sloped Bottom Electrode
US-2018287057-A1 · Oct 4, 2018 · US
Resistive memory cell with sloped bottom electrode
US-10003021-B2 · Jun 19, 2018 · US
Resistive memory cell having a reduced conductive path area
US-9917251-B2 · Mar 13, 2018 · US
Resistive memory cell having a single bottom electrode and two top electrodes
US-9865814-B2 · Jan 9, 2018 · US
Method for forming resistive memory cell having a spacer region under an electrolyte region and a top electrode
US-9865813-B2 · Jan 9, 2018 · US
Forming fence conductors using spacer etched trenches
US-9583435-B2 · Feb 28, 2017 · US
Resistive Memory Cell Having A Reduced Conductive Path Area
US-2016315257-A1 · Oct 27, 2016 · US
Spacer Enabled Poly Gate
US-2016314978-A1 · Oct 27, 2016 · US
Resistive memory cell with bottom electrode having a sloped side wall
US-9412942-B2 · Aug 9, 2016 · US
Resistive memory cell having a reduced conductive path area
US-9385313-B2 · Jul 5, 2016 · US
Spacer enabled poly gate
US-9385043-B2 · Jul 5, 2016 · US
Resistive Memory Cell With Sloped Bottom Electrode
US-2016190441-A1 · Jun 30, 2016 · US
Resistive Memory Cell Having A Reduced Conductive Path Area
US-2016190442-A1 · Jun 30, 2016 · US
Resistive memory cell with trench-shaped bottom electrode
US-9362496-B2 · Jun 7, 2016 · US
Resistive memory cell having a reduced conductive path area
US-9318702-B2 · Apr 19, 2016 · US
Resistive Memory Cell Having A Spacer Region For Reduced Conductive Path Area / Enhanced Electric Field
US-2016079527-A1 · Mar 17, 2016 · US
Spacer enabled active isolation for an integrated circuit device
US-9269606-B2 · Feb 23, 2016 · US
Forming fence conductors using spacer etched trenches
US-2015249050-A1 · Sep 3, 2015 · US
Resistive Memory Cell with Sloped Bottom Electrode
US-2015236256-A1 · Aug 20, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Microchip Tech Inc | 35 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H01L45/1273 | 17 |
| H10N70/8418 | 17 |
| H10N70/8822 | 17 |
| H10N70/011 | 17 |
| H10N70/8828 | 17 |