Burst mode read controllable SRAM

Patent metadata

Field	Value
Publication number	US-9613685-B1
Application number	US-201514940715-A
Country	US
Kind code	B1
Filing date	Nov 13, 2015
Priority date	Nov 13, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to receive a precharge signal and a word line signal and identify consecutive reads from storage cells accessed via a same one of the word lines. The read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines after each read of the consecutive reads.

First claim

What is claimed is:

1. A static random access memory (SRAM), comprising:
an array of storage cells arranged as rows and columns, and comprising word lines that correspond to the rows and bit lines that correspond to the columns; and
a read controller to manage reading from the storage cells, the read controller configured to:
receive a precharge signal and a word line pulse signal;
identify consecutive reads from storage cells accessed via a same one of the word lines; and
based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads, and charge the same one of the word lines after each read of the consecutive reads.

2. The SRAM of claim 1 wherein the read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a full burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines no more than once during the consecutive reads.

3. The SRAM of claim 2 wherein the read controller is further configured to identify that the SRAM is to operate in a full burst mode by determining that the precharge signal is at a same state as the word line pulse signal.

4. The SRAM of claim 1 wherein the read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a no burst mode, precharge the bit lines after each read of the consecutive reads.

5. The SRAM of claim 1 wherein the read controller is further configured to perform a precharge of the bit lines at a start of the consecutive reads.

6. The SRAM of claim 1 , wherein the read controller is further configured to perform a precharge of the bit lines at an end of the consecutive reads.

7. The SRAM of claim 1 , wherein, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, the read controller is further configured to perform only a single precharge of the bit lines in conjunction with the consecutive reads.

8. The SRAM of claim 1 , further comprising:
a column decoder configured to receive an output signal from each of the columns and select the output signal from the column corresponding to the storage cell being read, each of the output signals corresponding to a differential voltage in each of the columns; and
a sense amplifier configured to determine a state of the selected column by sensing the column voltage differential for the selected column.

9. A method for reducing power consumption in static random access memory (SRAM), comprising:
precharging a plurality of bit lines of an array of storage cells arranged as rows and columns, the plurality of bit lines corresponding to the columns;
charging a first word line of the array of storage cells, the first word line corresponding to a first of the rows;
identifying consecutive reads from the storage cells accessed via the first word line;
reading, as part of the consecutive reads, a first storage cell and a second storage cell without precharging the bit lines between the reading of the first and second storage cells; and
charging the first word line after each read of the consecutive reads.

10. The method of claim 9 , wherein the reading the first and second storage cells comprises:
detecting a column voltage differential between two bit lines connected to the first storage cell; and
detecting a column voltage differential between two bit lines connected to the second storage cell.

11. The method of claim 9 , further comprising, receiving a precharge signal and a word line pulse signal, wherein the pulsing the first word line after each read of the consecutive reads is based on a determination that the precharge signal and the word line pulse signal indicate that the SRAM is to operate in a partial burst mode.

12. The method of claim 11 , further comprising, based on a determination that the precharge signal and the word line pulse signal indicate that the SRAM is to operate in a no burst mode, precharging the bit lines after each read of the consecutive reads.

13. The method of claim 11 , further comprising, based on a determination that the precharge signal and the word line pulse signal indicate that the SRAM is to operate in a full burst mode, charge the first word line no more than once during the consecutive reads.

14. The method of claim 9 , further comprising:
precharging the bit lines at a start of the consecutive reads; and
precharging the bit lines at an end of the consecutive reads.

15. An integrated circuit, comprising:
a processor;
a read mode signal generator configured to generate a precharge signal and a word line pulse signal; and
a static random access memory (SRAM) coupled to the processor and the read mode signal generator, the SRAM comprising:
an array of storage cells arranged as rows and columns, the SRAM comprising word lines that correspond to the rows and bit lines that correspond to the columns; and
a read controller to manage reading from the storage cells, the read controller comprising:
precharge circuitry configured to identify consecutive reads to storage cells accessed via a same one of the word lines and, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines on fewer than all the consecutive reads; and
word line pulse circuitry configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in the partial burst mode, charge the same one of the word lines after each read of the consecutive reads.

16. The integrated circuit of claim 15 , wherein the read mode signal generator is programmable.

17. The integrated circuit of claim of claim 15 wherein the read mode signal generator comprises a temperature sensor and is further configured to generate the precharge signal and the word pulse signal based on a temperature sensed by the temperature sensor.

18. The integrated circuit of claim 17 , wherein the read mode signal generator is further configured to generate the precharge signal and the word pulse signal indicating that the SRAM is to operate in a no burst mode based on the temperature sensed by the temperature sensor exceeding a threshold value.

19. The integrated circuit of claim 15 , wherein:
the precharge circuitry is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a full burst mode, precharge the bit lines no more than once during the consecutive reads; and
the word line pulse circuitry if further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in the full burst mode, charge the same one of the word lines no more than once during the consecutive reads.

20. The integrated circuit of claim 15 , wherein:
the precharge circuitry is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a no burst mode, precharge the bit lines after each read of the consecutive reads.

Assignees

• Texas Instruments Inc

Inventors

• Seetharaman Premkumar
• Menezes Vinod

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title