Circuits and methods for performance optimization of sram memory

Patent metadata

Field	Value
Publication number	US-2016163379-A1
Application number	US-201414562056-A
Country	US
Kind code	A1
Filing date	Dec 5, 2014
Priority date	Dec 5, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

First claim

1 . (canceled)

2 . The circuitry for data storage of claim 7 , wherein the SRAM circuit further comprises:
an address input operable for receiving an address indicating one or more particular SRAM cells are to be accessed; a read/write input operable for receiving a read/write control signal indicating whether an access to the SRAM circuit is a read or a write access; a data input operable for receiving write data to be written into one or more SRAM cells within the SRAM circuit; a data output signal operable for outputting read data retrieved from one or more cells within the SRAM circuit; a row decoder circuit operable for receiving a portion of the address input and outputting a row select voltage on one of the plurality of word lines for a selected row of SRAM cells that is indicated by the portion of the address input; a column decoder circuit operable for decoding a second portion of the address input and outputting Y-select signals corresponding to a column of SRAM cells indicated by the second portion of the address input; and a column select multiplexer operable for receiving the Y-select signals and operable to couple a pair complementary bit lines corresponding to the column indicated by the second portion of the address input signal to one of a plurality of sense amplifiers, the sense amplifiers each operable to sense a differential voltage present on the pair of complementary bit lines and to amplify the differential voltage and further operable to output a logic level voltage to the data output signal.

3 . (canceled)

4 . A circuit for data storage, comprising:
a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell circuit coupled to one of a plurality of word lines disposed along the rows of SRAM cell circuits, and each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, the SRAM cell circuits each operable to output a differential voltage corresponding to a stored datum on the corresponding pair of complementary bit lines responsive to a row select voltage on the word line coupled to the SRAM cell circuit, and one or more precharge circuits in the SRAM circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal; and a memory controller circuit external to and coupled to the SRAM circuit and operable to control read and write data accesses to the SRAM circuit by outputting one or more precharge control signals to the SRAM circuit; wherein the precharge control signal within the SRAM circuit is operable to cause coupling transistors within the precharge circuits of the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage, responsive to the precharge control signals output from external memory controller circuit indicating a bitline precharge is to be performed; wherein the memory controller circuit further comprises precharge mode control circuitry operable to output; a burst mode enable signal to the SRAM circuit indicating that a next memory address to be accessed is to a memory cell along the same row as the current row corresponding to the current address input to the SRAM circuit; a precharge first mode signal to the SRAM circuit when a sequence of SRAM memory accesses will occur along the same row of SRAM cells; and precharge last mode signal to the SRAM circuit when a sequence of SRAM memory accesses will occur that requires access to a row of SRAM cells that differs from the row of SRAM cells that is currently being accessed.

5 . The circuit for data storage of claim 4 , wherein the SRAM circuit further comprises:
bitline precharge circuitry operable to couple the bit lines in the SRAM memory to a precharge voltage prior to each memory access in a conventional mode, the bitline precharge circuitry responsive to a first state on the burst mode enable signal.

6 . The circuit for data storage of claim 4 , wherein the SRAM circuit further comprises:
bitline precharge circuitry operable to couple the bit lines in the SRAM memory to the precharge voltage during a first access to SRAM cells along a selected word line, and operable to not couple the bit lines to the precharge voltage during subsequent accesses along a selected word line, responsive to a second state on the burst mode enable signal.

7 . A circuit for data storage, comprising:
a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell circuit coupled to one of a plurality of word lines disposed along the rows of SRAM cell circuits, and each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, the SRAM cell circuits each operable to output a differential voltage corresponding to a stored datum on the corresponding pair of complementary bit lines responsive to a row select voltage on the word line coupled to the SRAM cell circuit, and one or more precharge circuits in the SRAM circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal; and a memory controller circuit external to and coupled to the SRAM circuit and operable to control read and write data accesses to the SRAM circuit by outputting one or more precharge control signals to the SRAM circuit; wherein the precharge control signal within the SRAM circuit is operable to cause coupling transistors within the precharge circuits of the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage, responsive to the precharge control signals output from external memory controller circuit indicating a bitline precharge is to be performed; wherein the memory controller circuit further comprises high frequency precharge mode control circuitry operable to output precharge control signals to the SRAM circuit when a clocking frequency over a predetermined threshold is detected.

8 . The circuit for data storage of claim 7 , wherein the high frequency precharge mode control circuitry in the memory controller circuit is further operable to output a precharge only cycle control signal to the SRAM circuit.

9 . The circuit for data storage of claim 7 , wherein the memory controller circuit further comprises low frequency precharge control circuitry operable to output signals for controlling precharge cycles in the SRAM circuit when a clock signal has a frequency lower than a predetermined threshold.

10 . The circuit for data storage of claim 9 , wherein the low frequency precharge control circuitry is further operable to output a burst mode enable signal indicating a sequence of memory accesses to SRAM cells in the SRAM circuit along a same row and coupled to a same word line in the SRAM circuit.

11 . The circuit for data storage of claim 10 wherein the low frequency precharge control circuitry is further operable to output a precharge first control signal to the SRAM circuit indicating a bitline precharge is to be performed by the SRAM circuit for the first memory access in a sequence of memory accesses.

12 . (canceled)

13 . The method of claim 16 , wherein in the burst mode, the precharge circuit is operated once prior to a first SRAM cell access in the series of accesses.

14 . The method of claim 16 , wherein in the burst mode, the precharge circuit is operated once following a last SRAM cell access in the s

Assignees

• Texas Instruments Inc

Inventors

• Roine Per Torstein
• Menezes Vinod
• Mehendale Mahesh
• Gullapalli Vamsi
• Seetharaman Premkumar

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C7/1018

  Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title