Method for manufacturing wiring board, and wiring board

Patent metadata

Field	Value
Publication number	US-2021084774-A1
Application number	US-202017017984-A
Country	US
Kind code	A1
Filing date	Sep 11, 2020
Priority date	Sep 18, 2019
Publication date	Mar 18, 2021
Grant date	—

Abstract

Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.

First claim

What is claimed is:

1 . A method for manufacturing a wiring board including an insulating substrate, and a wiring layer with a predetermined wiring pattern disposed on the surface of the insulating substrate, the method comprising:
preparing a substrate with seed-layer, the substrate with seed-layer including: an electrically conductive underlayer on the surface of the insulating substrate; and a seed layer with a predetermined pattern corresponding to the wiring pattern on the surface of the underlayer, the seed layer containing metal; disposing a solid electrolyte membrane between an anode and the seed layer as a cathode, pressing the solid electrolyte membrane against the seed layer and the underlayer, and applying voltage between the anode and the underlayer to reduce metal ions contained in the solid electrolyte membrane and so form a metal layer on the surface of the seed layer; and removing an exposed region of the underlayer without the seed layer and the metal layer to form the wiring layer including the underlayer, the seed layer and the metal layer on the surface of the insulating substrate, and so manufacture the wiring board, during formation of the metal layer on the surface of the seed layer, at least a region of the surface of the underlayer, on which the seed layer is not formed, containing oxide.

2 . The method for manufacturing the wiring board according to claim 1 , wherein during formation of the metal layer on the surface of the seed layer, a natural oxide film including the oxide is formed in at least a region of the surface of the underlayer, on which the seed layer is not formed.

3 . The method for manufacturing the wiring board according to claim 1 , wherein when copper sulfate solution with concentration of 1 mol/L at a temperature of 25° C. is used as an electrolyte, oxygen-free copper wire is used as a counter electrode, a saturated calomel electrode is used as a reference electrode, and a first polarization curve using the material of the underlayer as a working electrode and a second polarization curve using the metal of the seed layer as a working electrode are measured while setting a potential sweep rate at 10 mV/sec, potential of the first polarization curve at a current density of 0.1 mA/cm 2 is higher than potential of the second polarization curve at a current density of 0.1 mA/cm 2 by 0.02 V or more.

4 . The method for manufacturing the wiring board according to claim 1 , wherein when preparing the substrate with seed-layer,
the method prepares a substrate including a surface with center-line average roughness Ra of 1 μm or less as the insulating substrate, and forms the underlayer by sputtering on the surface of the insulating substrate.

5 . The method for manufacturing the wiring board according to claim 4 , wherein the seed layer is formed on the surface of the underlayer so that line/space is 2 μm or more and 100 μm or less/2 μm or more and 100 μm or less.

6 . The method for manufacturing the wiring board according to claim 1 , wherein when preparing the substrate with seed-layer, the method places ink containing metal nanoparticles on the surface of the underlayer, and then sinters the metal nanoparticles to form the seed layer.

7 . The method for manufacturing the wiring board according to claim 1 , wherein when preparing the substrate with seed-layer, the method forms the seed layer on the surface of the underlayer so that the predetermined pattern of the seed layer has a plurality of independent patterns that are spaced away from each other.

8 . A wiring board comprising an insulating substrate, and a wiring layer with a predetermined wiring pattern disposed on the surface of the insulating substrate,
the wiring layer including the lamination of: an electrically conductive underlayer disposed on the surface of the insulating substrate; a seed layer disposed on the surface of the underlayer and containing metal; and a metal layer disposed on the surface of the seed layer, the seed layer including a side face extending from a laminated surface that is the surface of the seed layer toward the underlayer, the metal layer covering the surface and the side face of the seed layer, at least a region of the surface of the underlayer, on which the seed layer is not formed, containing oxide.

9 . The wiring board according to claim 8 , wherein the metal layer on the surface of the seed layer has a thickness that is larger than a thickness of the metal layer on the side face.

10 . The wiring board according to claim 8 , wherein the wiring layer has a taper shape that tapers in accordance with a distance from the insulating substrate in a portion closer to the insulating substrate than the surface of the seed layer, and has a reverse taper shape that becomes thicker in accordance with a distance from the insulating substrate in a portion farther from the insulating substrate than the surface of the seed layer, and
the wiring layer has a width of the taper-shaped part that is smaller than a width of the reverse taper-shaped part.

11 . The wiring board according to claim 8 , wherein the seed layer has line/space of 2 μm or more and 100 μm or less/2 μm or more and 100 μm or less.

Assignees

• Toyota Motor Co Ltd

Inventors

• Okamoto Kazuaki
• Yanagimoto Hiroshi
• Mori Rentaro

Classifications

• H05K3/4007 Primary

  Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465) · CPC title

• H05K3/383

  by microetching · CPC title

• H05K2203/0502

  Patterning and lithography · CPC title

• H05K3/182 Primary

  characterised by the patterning method · CPC title

• C25D3/38

  of copper · CPC title