Snubber Circuit and Power Semiconductor Module with Snubber Circuit

Patent metadata

Field	Value
Publication number	US-2021006062-A1
Application number	US-202016919518-A
Country	US
Kind code	A1
Filing date	Jul 2, 2020
Priority date	Jul 5, 2019
Publication date	Jan 7, 2021
Grant date	—

Abstract

A snubber circuit includes a snubber substrate including an electrically insulating carrier and an electrically conducting structured layer applied thereon, the electrically conducting structured layer including two segments. The snubber circuit fuither includes two electrically resistive layers, each resistive layer being applied onto the two segments of the electrically conducting structured layer of the snubber substrate, and a capacitor disposed on the electrically resistive layers and having two terminals, each terminal being electrically connected to one of the electrically resistive layers. Further, a power semiconductor module having such a snubber circuit is disclosed.

First claim

What is claimed is:

1 . A snubber circuit, comprising:
a snubber substrate comprising an electrically insulating carrier and an electrically conducting structured layer applied thereon, the electrically conducting structured layer of the snubber substrate including two segments; two electrically resistive layers, each resistive layer being applied onto the two segments of the electrically conducting structured layer of the snubber substrate; and a capacitor disposed on the electrically resistive layers and having two terminals, each terminal being electrically connected to one of the electrically resistive layers.

2 . The snubber circuit of claim L further comprising:
first electrically conductive interconnecting layers disposed between the two electrically resistive layers and the two segments of the electrically conducting structured layer of the snubber substrate.

3 . The snubber circuit of claim 2 , wherein the first electrically conductive interconnecting layers are configured to have the effect of a heat capacitance.

4 . The snubber circuit of claim 2 , further comprising:
second electrically conductive interconnecting layers disposed between the two electrically resistive layers and the two terminals of the capacitor.

5 . The snubber circuit of claim 4 , wherein the second electrically conductive interconnecting layers are configured to have the effect of a heat capacitance.

6 . The snubber circuit of claim 1 , wherein the two electrically resistive layers have a resistivity of more than 0.03 Ωm.

7 . The snubber circuit of claim 6 , wherein the electrically resistive layers comprise material with a homogenous resistivity distribution.

8 . The snubber circuit of claim 1 , wherein the two electrically resistive layers have a height that is equal to or less than ⅕ of the square root of a basic area of the respective electrically resistive layer.

9 . The snubber circuit of claim 8 , wherein the electrically resistive layers comprise material with a homogenous resistivity distribution.

10 . The snubber circuit of claim 1 , wherein the two electrically resistive layers comprise doped semiconductor material.

11 . The snubber circuit of claim 1 , wherein the terminals of the capacitor are arranged at lateral ends of the capacitor and have a shape of a cuboid end cap.

12 . The snubber circuit of claim 1 , wherein the terminals of the capacitor are arranged at lateral ends of the capacitor and have an L-shape.

13 . A power semiconductor module, comprising:
a module substrate comprising an electrically insulating carrier and an electrically conducting structured module layer applied thereon, the electrically conducting structured. layer including multiple segments; at least one semiconductor switching device disposed on the module substrate and electrically connected to the electrically conducting structured layer; and at least one snubber circuit disposed on the module substrate and connected via the electrically conducting structured layer of the module substrate to the at least one semiconductor switching device, the at least one snubber circuit comprising:
a snubber substrate comprising an electrically insulating carrier and an electrically conducting structured layer applied thereon, the electrically conducting structured layer of the snubber substrate including two segments;
two electrically resistive layers, each resistive layer being applied onto the two segments of the electrically conducting structured layer of the snubber substrate; and
a capacitor disposed on the electrically resistive layers and having two terminals, each terminal being electrically connected to one of the electrically resistive layers.

14 . The power semiconductor module of claim 13 , wherein the at least one snubber circuit is disposed in close proximity to the at least one semiconductor switching device.

15 . The power semiconductor module of claim 13 , wherein the snubber substrate is part of the module substrate.

16 . The power semiconductor module of claim 13 , wherein the at least one semiconductor switching device is a silicon-carbide metal-oxide field-effect transistor.

17 . The power semiconductor module of claim 13 , wherein the at least one snubber circuit further comprises a snubber diode.

18 . The power semiconductor module of claim 13 , wherein the at least one snubber circuit is disposed in the center of the module substrate.

Assignees

• Infineon Technologies Ag

Inventors

• Schlueter Michael
• Uhlemann Andre

Classifications

• H10D62/8325

  Silicon carbide · CPC title

• H02M1/348

  Passive dissipative snubbers · CPC title

• H05K1/162

  incorporating printed capacitors · CPC title

• H05K1/182

  associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] · CPC title

• H03K19/0185

  using field effect transistors only · CPC title