Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2020083801-A1
Application number	US-201916450115-A
Country	US
Kind code	A1
Filing date	Jun 24, 2019
Priority date	Sep 12, 2018
Publication date	Mar 12, 2020
Grant date	—

Abstract

The object is to provide a technology for enabling detection of the voltage resistance in an assembled snubber substrate. A semiconductor device includes: a snubber substrate fixed to a base while being spaced from a p electrode and an n electrode; a snubber circuit disposed on the snubber substrate and electrically connected to the p electrode and the n electrode; and a semiconductor element electrically connected to the snubber circuit. The base includes an insulating component insulating the p electrode, the n electrode, and the snubber substrate from one another.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a base; a p electrode with a positive conductor pattern, and an n electrode with a negative conductor pattern, the p electrode and the n electrode being disposed on the base with a spacing; a snubber substrate fixed to the base while being spaced from the p electrode and the n electrode; a snubber circuit disposed on the snubber substrate and electrically connected to the p electrode and the n electrode; and a semiconductor element electrically connected to the snubber circuit, wherein the base includes an insulating component insulating the p electrode, the n electrode, and the snubber substrate from one another.

2 . The semiconductor device according to claim 1 ,
wherein the insulating component includes an insulating ceramic substrate, and the p electrode, the n electrode, and the snubber substrate are fixed to the ceramic substrate.

3 . The semiconductor device according to claim 1 ,
wherein the base further includes a base plate, the snubber substrate is fixed above the base plate, and the insulating component includes: an insulating first ceramic substrate disposed between the base plate and the p electrode; and an insulating second ceramic substrate disposed between the base plate and the n electrode.

4 . The semiconductor device according to claim 1 ,
wherein the base further includes a metal pattern insulated by the insulating component from the p electrode and the n electrode, and the snubber substrate is fixed to the metal pattern.

5 . The semiconductor device according to claim 4 ,
wherein the base further includes a base plate electrically connected to the metal pattern, and the metal pattern is fixed above the base plate.

6 . The semiconductor device according to claim 5 ,
wherein the insulating component includes an insulating ceramic substrate disposed between the metal pattern and the base plate, and the metal pattern is electrically connected to the base plate through a through hole formed in the ceramic substrate.

7 . The semiconductor device according to claim 1 , further comprising
a bonding material for fixing the snubber substrate to the base, the bonding material containing silicone.

8 . The semiconductor device according to claim 1 ,
wherein the semiconductor element contains silicon or a wide bandgap semiconductor.

9 . A method for manufacturing the semiconductor device according to claim 1 ,
wherein the snubber substrate is an insulating ceramic substrate, the method comprising printing a paste and a conductor on the snubber substrate, and forming a resistor by firing the paste to form the snubber circuit.

10 . A method for manufacturing the semiconductor device according to claim 1 , the method comprising
fixing the semiconductor element to the base, and then fixing the snubber substrate to the base.

Assignees

• Mitsubishi Electric Corp

Inventors

• Shimizu Yasutaka
• Miyazaki Yuji
• Okada Kazuya

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H02M7/003

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• H02M7/5387

  in a bridge configuration · CPC title

• H02M7/48

  using discharge tubes with control electrode or semiconductor devices with control electrode · CPC title

• H02M1/34 Primary

  Snubber circuits · CPC title