Wafer holder

US2020340102A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020340102-A1
Application numberUS-201816498853-A
CountryUS
Kind codeA1
Filing dateFeb 8, 2018
Priority dateMar 28, 2017
Publication dateOct 29, 2020
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A wafer holder comprising: a ceramic base having a wafer-mounting surface as an upper surface; and a conductive member embedded in the ceramic base, the conductive member including a circuit portion provided parallel to the wafer-mounting surface, a pull-out portion provided parallel to the wafer-mounting surface and spaced from the circuit portion in a direction opposite to a direction toward the wafer-mounting surface, and a connecting portion configured to electrically connect the circuit portion and the pull-out portion to each other.

First claim

Opening claim text (preview).

1 . A wafer holder comprising: a ceramic base having a wafer-mounting surface as an upper surface; and a conductive member embedded in the ceramic base, the conductive member including a circuit portion provided parallel to the wafer-mounting surface, a pull-out portion provided parallel to the wafer-mounting surface and spaced from the circuit portion in a direction opposite to a direction toward the wafer-mounting surface, and a connecting portion configured to electrically connect the circuit portion and the pull-out portion to each other. 2 . The wafer holder according to claim 1 , further comprising: a cylindrical support configured to support a lower surface of the ceramic base; and an electrode terminal portion connected to the pull-out portion, wherein a portion of the electrode terminal portion protrudes from the lower surface of the ceramic base and is housed in the cylindrical support. 3 . The wafer holder according to claim 1 , wherein the conductive member constitutes an RF electrode or a resistance heating element. 4 . The wafer holder according to claim 1 , comprising a plurality of the conductive members, each of the plurality of the conductive members constituting an RF electrode or a resistance heating element. 5 . The wafer holder according to claim 1 , further comprising: a second circuit portion embedded in the ceramic base and provided parallel to the wafer-mounting surface; and a second electrode terminal portion connected to the second circuit portion, wherein a portion of the second electrode terminal portion protrudes from the lower surface of the ceramic base. 6 . The wafer holder according to claim 5 , wherein the second circuit portion is an RF electrode or a resistance heating element or an electrostatic chuck electrode. 7 . The wafer holder according to claim 1 , wherein the connecting portion is a ceramic member covered with a metal layer. 8 . The wafer holder according to claim 1 , wherein the ceramic base has a disk shape. 9 . The wafer holder according to claim 2 , wherein the cylindrical support has a circular cylindrical shape.

Assignees

Inventors

Classifications

  • H10P72/72Primary

    using electrostatic chucks · CPC title

  • in the presence of a plasma [PECVD] · CPC title

  • mainly by conduction · CPC title

  • Elements in the interior of the support, e.g. electrodes, heating or cooling devices · CPC title

  • C23C16/458Primary

    characterised by the method used for supporting substrates in the reaction chamber · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2020340102A1 cover?
A wafer holder comprising: a ceramic base having a wafer-mounting surface as an upper surface; and a conductive member embedded in the ceramic base, the conductive member including a circuit portion provided parallel to the wafer-mounting surface, a pull-out portion provided parallel to the wafer-mounting surface and spaced from the circuit portion in a direction opposite to a direction toward …
Who is the assignee on this patent?
Sumitomo Electric Industries
What technology area does this patent fall under?
Primary CPC classification H10P72/72. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 29 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).