Method for forming embedded grounding planes on interconnect layers

Patent metadata

Field	Value
Publication number	US-2020328131-A1
Application number	US-201916380486-A
Country	US
Kind code	A1
Filing date	Apr 10, 2019
Priority date	Apr 10, 2019
Publication date	Oct 15, 2020
Grant date	—

Abstract

Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

First claim

What is claimed is:

1 . An electronic package, comprising:
a substrate layer; a trace over the substrate layer; a first pad over the substrate layer; a solder resist over the trace and the first pad; a trench into the solder resist, the trench extending over the trace; and a conductive plate in the trench, wherein the conductive plate is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

2 . The electronic package of claim 1 , wherein the trace has a first end and a second end, and wherein the conductive plate covers the trace from the first end to the second end.

3 . The electronic package of claim 2 , wherein the first pad is laterally adjacent to the trace.

4 . The electronic package of claim 1 , further comprising a solder resist opening (SRO) through the solder resist, the solder resist opening exposing a surface of a second pad.

5 . The electronic package of claim 4 , further comprising:
a solder bump in the SRO.

6 . The electronic package of claim 4 , wherein a surface finish is over the surface of the second pad.

7 . The electronic package of claim 6 , wherein a surface finish is over a surface of the conductive plate.

8 . The electronic package of claim 1 , wherein the conductive plate is electrically coupled to a plurality of first pads by a plurality vias.

9 . The electronic package of claim 1 , wherein a thickness of solder resist between a bottom surface of the conductive plate and a top surface of the trace is between 2 μm and 145 μm.

10 . The electronic package of claim 1 , further comprising a seed layer between the conductive plate and the solder resist.

11 . The electronic package of claim 10 , wherein the seed layer is present between the via and the first pad.

12 . The electronic package of claim 1 , wherein the solder resist comprises palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, or tantalum particles.

13 . The electronic package of claim 1 , wherein the first pad is a ground pad.

14 . The electronic package of claim 1 , wherein the trace is for propagating signals.

15 . A method of fabricating an electronic package, comprising:
disposing a solder resist over a substrate layer, wherein a first pad, a second pad, and a trace are positioned over the substrate layer; forming a solder resist opening (SRO) through the solder resist to expose the second pad; forming a mask over the solder resist and the exposed second pad; forming a trench into the solder resist, wherein the trench extends over the trace; forming a via opening to expose the first pad, wherein the via opening is within a footprint of the trench; disposing a seed layer into the trench and the via opening; disposing a via in the via opening and a plate in the trench; and removing the mask.

16 . The method of claim 15 , wherein the mask comprises TiO 2 .

17 . The method of claim 16 , wherein forming the mask, comprises:
disposing a titanium layer; and oxidizing the titanium layer to form a TiO 2 surface.

18 . The method of claim 16 , wherein the seed layer comprises palladium, and wherein the palladium does not adsorb to the TiO 2 .

19 . The method of claim 16 , wherein disposing the via in the via opening and the plate in the trench comprises an electroless deposition process.

20 . The method of claim 16 , wherein disposing the via in the via opening and the plate in the trench comprises an electrolytic deposition process.

21 . The method of claim 15 , wherein the solder resist comprises palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, or tantalum particles, and wherein the seed layer is disposed during a laser ablation process used to form the trench and the via opening.

22 . The method of claim of claim 15 , further comprising:
disposing a surface finish over the second pad and the plate.

23 . An electronic system, comprising:
an electronic package, the electronic package comprising:
a substrate;
a first pad over the substrate;
a trace over the substrate;
a solder resist over the first pad and the trace;
a trench into the solder resist, the trench extending over the trace; and
a conductive plate in the trench, wherein the conductive plate is electrically coupled to the first pad by a via; and
a die electrically coupled to the electronic package.

24 . The electronic package of claim 23 , wherein the electronic package is electrically coupled to a board.

25 . The electronic package of claim 23 , wherein the first pad is laterally adjacent to the trace, wherein the trace has a first end and a second end, and wherein the conductive plate covers the trace from the first end to the second end.

Assignees

• Intel Corp

Inventors

• Marin Brandon C
• Darmawikarta Kristof
• Dittler Roy
• Ecton Jeremy
• Grujicic Darko

Classifications

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title