Nanowire interfaces

Patent metadata

Field	Value
Publication number	US-2020321303-A1
Application number	US-202016843580-A
Country	US
Kind code	A1
Filing date	Apr 8, 2020
Priority date	Apr 8, 2019
Publication date	Oct 8, 2020
Grant date	—

Abstract

In some examples, a system comprises a first component having a first surface, a first set of nanoparticles coupled to the first surface, and a first set of nanowires extending from the first set of nanoparticles. The system also comprises a second component having a second surface, a second set of nanoparticles coupled to the second surface, and a second set of nanowires extending from the second set of nanoparticles. The system further includes an adhesive positioned between the first and second surfaces. The first and second sets of nanowires are positioned within the adhesive.

First claim

What is claimed is:

1 . A system, comprising:
a first component having a first surface; a first set of nanoparticles coupled to the first surface; a first set of nanowires extending from the first set of nanoparticles; a second component having a second surface; a second set of nanoparticles coupled to the second surface; a second set of nanowires extending from the second set of nanoparticles; and an adhesive positioned between the first and second surfaces, the first and second sets of nanowires positioned within the adhesive.

2 . The system of claim 1 , further comprising a metal layer positioned on the first surface, the first set of nanoparticles positioned on the metal layer.

3 . The system of claim 1 , further comprising a metal layer positioned on the second surface, the second set of nanoparticles positioned on the metal layer.

4 . The system of claim 1 , wherein the adhesive is selected from the group consisting of a glue, an epoxy, and solder.

5 . The system of claim 1 , wherein the first component comprises a semiconductor die and the second component comprises a lead frame die pad.

6 . The system of claim 1 , wherein a nanowire of the first set of nanowires has a length-to-width ratio of at least 2 to 1.

7 . The system of claim 1 , wherein a nanowire of the first set of nanowires has a diameter ranging between 0.5 microns and 1.5 microns.

8 . The system of claim 1 , wherein a nanoparticle of the first set of nanoparticles has a diameter ranging between 0.01 microns and 1.5 microns.

9 . The system of claim 1 , further comprising a third component coupled to the first component, the third component having a third set of nanowires coupled thereto.

10 . A semiconductor package, comprising:
a semiconductor die; a first metal layer coupled to the semiconductor die; a first set of nanowires coupled to the first metal layer; a die pad; a second metal layer coupled to the die pad; a second set of nanowires coupled to the second metal layer; and an adhesive between the semiconductor die and the die pad, the first and second sets of nanowires positioned within the adhesive.

11 . The semiconductor package of claim 10 , wherein the first metal layer comprises a set of nanoparticles.

12 . The semiconductor package of claim 10 , wherein the first metal layer is a solid metal layer.

13 . The semiconductor package of claim 10 , further comprising a conductive terminal exposed to an exterior surface of the package, the conductive terminal coupled to the semiconductor die, a third set of nanowires coupled to a third metal layer, the third metal layer positioned on the conductive terminal.

14 . The semiconductor package of claim 13 , wherein the third metal layer comprises a set of nanoparticles.

15 . The semiconductor package of claim 13 , further comprising a clip coupled to the conductive terminal, the clip coupled to the semiconductor die using a second adhesive, the clip having a third set of nanowires coupled thereto and positioned within the second adhesive.

16 . The semiconductor package of claim 15 , further comprising a fourth set of nanowires coupled to a surface of the die opposite a surface of the semiconductor die to which the first set of nanowires is coupled, the fourth set of nanowires positioned within the second adhesive.

17 . The semiconductor package of claim 10 , wherein the adhesive is selected from the group consisting of epoxy, glue, and solder.

18 . A method, comprising:
forming a first metal layer on a semiconductor wafer; plating a first set of nanowires on the first metal layer; singulating the semiconductor wafer to produce a semiconductor die; forming a second metal layer on a die pad; plating a second set of nanowires on the second metal layer; and coupling the semiconductor die to the die pad using an adhesive such that the first and second sets of nanowires are positioned within the adhesive.

19 . The method of claim 18 , wherein the first metal layer comprises a set of nanoparticles.

20 . The method of claim 18 , wherein the first metal layer comprises a solid metal layer.

Assignees

• Texas Instruments Inc

Inventors

• Koduri Sreenivasan Kalyani
• Cook Benjamin Stassen
• Muenster Ralf Jakobskrueger

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/01335

  by plating, e.g. electroless plating or electroplating · CPC title