Multichip power semiconductor device
US-9443760-B2 · Sep 13, 2016 · US
US2020105707A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2020105707-A1 |
| Application number | US-201916588127-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 30, 2019 |
| Priority date | Oct 2, 2018 |
| Publication date | Apr 2, 2020 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.
Opening claim text (preview).
1 . A multi-clip structure comprising: a first clip for die bonding; a second clip for die bonding; and a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together. 2 . The multi-clip structure of claim 1 , wherein the first clip is a load clip for a power die and the second clip is a sense clip for the power die or a gate clip for the power die. 3 . The multi-clip structure of claim 1 , further comprising: a third clip for die boding, wherein the retaining tape is fixed to the third clip. 4 . The multi-clip structure of claim 3 , wherein the first clip is a load clip for a power die, the second clip is a sense clip for the power die and the third clip is a gate clip for the power die. 5 . The multi-clip structure of claim 1 , wherein the first clip comprises a lower surface including a die bonding portion and an upper surface opposite the lower surface; the second clip comprises a lower surface including a die bonding portion and an upper surface opposite the lower surface; and the retaining tape engages with the upper surface of the first clip and with the upper surface of the second clip. 6 . The multi-clip structure of claim 1 , wherein the retaining tape comprises a film of an electrically insulating material coated by an adhesive. 7 . The multi-clip structure of claim 1 , wherein the retaining tape has a structural stability sufficient to hold the first clip and the second clip in alignment during a pick-and-place operation. 8 . A semiconductor device package comprising: a die carrier; a die mounted on the die carrier; a first clip bonded to a first electrode of the die; a second clip bonded to the first electrode or a second electrode of the die; and a mold compound encapsulating the die, the first clip and the second clip, wherein the first clip and the second clip are cast-in-place by the mold compound and are completely encapsulated by the mold compound. 9 . The semiconductor device package of claim 8 , further comprising: a retaining tape fixed to the first clip and to the second clip. 10 . The semiconductor device package of claim 8 , wherein the semiconductor device package is a wireless package. 11 . The semiconductor device package of claim 8 , wherein the die is a power die, the first clip is a load clip for the power die and the second clip is a sense clip for the power die or a gate clip for the power die. 12 . The semiconductor device package of claim 8 , further comprising: a first external terminal of the semiconductor device package; and a second external terminal of the semiconductor device package, wherein the first clip is bonded to the first external terminal and the second clip is bonded to the second external terminal. 13 . The semiconductor device package of claim 12 , wherein, the first and second external terminals are leads of a leadframe and the die carrier is a heat sink element and/or a die pad of the leadframe. 14 . A method of attaching a multi-clip structure to a die, the method comprising: providing a multi-clip structure comprising a first clip for die bonding, a second clip for die bonding and a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together; and placing the multi-clip structure as one component over the die. 15 . The method of claim 14 , wherein placing is done by one pick-and-place operation. 16 . A method of manufacturing a semiconductor device package, the method comprising: placing a die on a die carrier; placing a multi-clip structure as one component over the die, wherein the multi-clip structure comprises a first clip for die bonding, a second clip for die bonding and a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together; attaching the multi-clip structure to the die and to external terminals of the semiconductor device package; and encapsulating the die and the multi-clip structure by cavity molding.
changes in structures or sizes · CPC title
Multiple strap connectors having different structures or shapes · CPC title
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
Encapsulations, e.g. protective coatings · CPC title
Die-attach connectors and strap connectors · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.