Power semiconductor module having low gate drive inductance flexible board connection

Patent metadata

Field	Value
Publication number	US-9355950-B1
Application number	US-201514592244-A
Country	US
Kind code	B1
Filing date	Jan 8, 2015
Priority date	Jan 8, 2015
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A power semiconductor module includes a metallization layer and a power semiconductor die attached to the metallization layer. The die has a first terminal and a second terminal disposed at a side of the die facing away from the metallization layer. The power semiconductor module further includes a first interconnect attached to the first terminal, a second interconnect attached to the second terminal and a flexible board including a first metal layer, a second metal layer and an insulator between the first and the second metal layers so that the first and the second metal layers are electrically insulated from one another. The first metal layer is attached to the first interconnect and the second metal layer is attached to the second interconnect such that the flexible board is spaced apart from the power semiconductor die by the first and the second interconnects.

First claim

What is claimed is:

1. A power semiconductor module, comprising:
a metallization layer;
a power semiconductor die attached to the metallization layer and having a first terminal and a second terminal disposed at a side of the die facing away from the metallization layer;
a first interconnect attached to the first terminal;
a second interconnect attached to the second terminal; and
a flexible board comprising a first metal layer, a second metal layer and an insulator between the first and the second metal layers so that the first and the second metal layers are electrically insulated from one another,
wherein the first metal layer is attached to the first interconnect and the second metal layer is attached to the second interconnect such that the flexible board is spaced apart from the power semiconductor die by the first and the second interconnects.

2. The power semiconductor module of claim 1 , wherein the first and the second interconnects are bond wires, bond ribbons or metal clips.

3. The power semiconductor module of claim 1 , wherein the first metal layer is welded to the first interconnect and the second metal layer is welded to the second interconnect.

4. The power semiconductor module of claim 1 , wherein:
the first metal layer of the flexible board is configured to carry a ground signal from an external driver;
the second metal layer of the flexible board is configured to carry a drive signal from the external driver;
the first terminal of the power semiconductor die is an emitter or source terminal; and
the second terminal of the power semiconductor die is a control or gate terminal.

5. The power semiconductor module of claim 4 , wherein one or more semiconductor dies and/or passive components of the external driver are attached to a section of the flexible board which protrudes out of a housing of the power semiconductor module.

6. The power semiconductor module of claim 1 , wherein:
the metallization layer has a plurality of sections separated from one another; and
the power semiconductor die is attached to a first one of the sections of the metallization layer at a side of the die facing the metallization layer.

7. The power semiconductor module of claim 6 , wherein:
the first interconnect has a first end attached to the first terminal of the semiconductor die and a second end attached to a second one of the sections of the metallization layer;
the second interconnect has a first end attached to the second terminal of the semiconductor die and a second end attached to a third one of the sections of the metallization layer;
the first metal layer of the flexible board is attached to a section of the first interconnect between the first and the second ends of the first interconnect; and
the second metal layer of the flexible board is attached to a section of the second interconnect between the first and the second ends of the second interconnect.

8. The power semiconductor module of claim 7 , wherein:
the second terminal of the power semiconductor die is an auxiliary emitter or source terminal;
the power semiconductor module further comprises a third interconnect having a first end attached to a main source or emitter terminal of the semiconductor die at the same side of the die as the auxiliary emitter or source terminal, and a second end attached to a fourth one of the sections of the metallization layer; and
the first and the second metal layers of the flexible board are not connected to the third interconnect.

9. The power semiconductor module of claim 1 , wherein:
the first interconnect has a first end attached to a first section of the first terminal of the semiconductor die and a second end attached to a second section of the first terminal; and
the first metal layer of the flexible board is attached to a section of the first interconnect between the first and the second ends of the first interconnect.

10. The power semiconductor module of claim 9 , wherein:
the second interconnect has a first end attached to a first section of the second terminal of the semiconductor die and a second end attached to a second section of the second terminal; and
the second metal layer of the flexible board is attached to a section of the second interconnect between the first and the second ends of the second interconnect.

11. The power semiconductor module of claim 9 , wherein:
the second terminal of the power semiconductor die is an auxiliary emitter or source terminal;
the power semiconductor module further comprises a third interconnect having a first end attached to a main source or emitter terminal of the semiconductor die at the same side of the die as the auxiliary emitter or source terminal, and a second end attached to the metallization layer; and
the first and the second metal layers of the flexible board are not connected to the third interconnect.

12. The power semiconductor module of claim 1 , wherein:
the first interconnect has a first end attached to the first terminal of the semiconductor die and a second end disposed on and attached to the first end; and
the first metal layer of the flexible board is attached to a section of the first interconnect between the first and the second ends of the first interconnect.

13. The power semiconductor module of claim 12 , wherein:
the second interconnect has a first end attached to the second terminal of the semiconductor die and a second end disposed on and attached to the first end; and
the second metal layer of the flexible board is attached to a section of the second interconnect between the first and the second ends of the second interconnect.

14. The power semiconductor module of claim 12 , wherein:
the second terminal of the power semiconductor die is an auxiliary emitter or source terminal;
the power semiconductor module further comprises a third interconnect having a first end attached to a main source or emitter terminal of the semiconductor die at the same side of the die as the auxiliary emitter or source terminal, and a second end attached to the metallization layer; and
the first and the second metal layers of the flexible board are not connected to the third interconnect.

15. The power semiconductor module of claim 1 , wherein the first interconnect has a first end attached to the first terminal of the semiconductor die and a second end attached to the first metal layer of the flexible board.

16. The power semiconductor module of claim 15 , wherein the second interconnect has a first end attached to the second terminal of the semiconductor die and a second end attached to the second metal layer of the flexible board.

17. The power semiconductor module of claim 15 , wherein:
the second terminal of the power semiconductor die is an auxiliary emitter or source terminal;
the power semiconductor module further comprises a third interconnect having a first end attached to a main source or emitter terminal of the semiconductor die at the same side of the die as the auxiliary emitter or source terminal, and a second end attached to the metallization layer; and
the first and the second metal layers of the flexible board are not connected to the third interconnect.

18. A power semiconductor module, comprising:
a patterned metallization layer having a plurality of sections separated from one another;
a plurality of power semiconductor dies attached at least to a first one of the sections of the patterned metallization layer and each having a first terminal and a second terminal disposed at a side of the die facing away from the patterned met

Assignees

• Infineon Technologies Ag

Inventors

• Bayerer Reinhold

Classifications

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W72/07652

  changes in structures or sizes · CPC title

• H10W72/627

  Multiple strap connectors having different structures or shapes · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title