Vertical fin field effect transistor with air gap spacers

Patent metadata

Field	Value
Publication number	US-2018053821-A1
Application number	US-201615243174-A
Country	US
Kind code	A1
Filing date	Aug 22, 2016
Priority date	Aug 22, 2016
Publication date	Feb 22, 2018
Grant date	—

Abstract

A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.

First claim

1 - 9 . (canceled).

10 . A method of forming a fin field effect transistor device with air gaps, comprising:
forming one or more vertical fins on a substrate; forming a source/drain layer on the substrate in contact with the one or more vertical fins on a substrate; forming a sacrificial bottom spacer on the source/drain layer; forming a sacrificial spacer cap on the sacrificial bottom spacer; forming a gate dielectric layer on at least a portion of the one or more vertical fins and the sacrificial spacer cap; forming a gate electrode on the gate dielectric layer; forming a U-shaped trough on the gate electrode; forming a sacrificial top spacer fill in the U-shaped trough; and removing the sacrificial bottom spacer to form a bottom void space between the source; drain layer and the sacrificial spacer cap.

11 . The method of claim 10 , wherein the sacrificial bottom spacer is silicon-germanium (Si x Ge 1−x ), silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), amorphous carbon (a-C), or combinations thereof.

12 . (canceled).

13 . The method of claim 10 , wherein the sacrificial top spacer fill is silicon nitride (SiN), amorphous carbon (a-C) amorphous silicon (a-Si), silicon-germanium (SiGe), or combinations thereof.

14 . The method of claim 13 , further comprising forming a top source/drain on the one or more vertical fins that spans the one or more vertical fins and covers a portion of the sacrificial top spacer fill.

15 . The method of claim 14 , further comprising removing the sacrificial top spacer fill to form an upper void space, wherein the top source/drain bounds the upper void space on one side and the U-shaped trough bounds the upper void space on three sides.

16 . The method of claim 15 , wherein the sacrificial top spacer fill is removed using an isotropic wet etch.

17 - 20 . (canceled).

Assignees

• IBM

Inventors

• Mallela Hari V
• Robison Robert R
• Vega Reinaldo A
• Venigalla Rajasekhar

Classifications

• H10D64/01334

  by defining the insulator using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall · CPC title

• H10D64/0133

  at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title