Vertical transistors having different gate lengths

Patent metadata

Field	Value
Publication number	US-9653465-B1
Application number	US-201615262347-A
Country	US
Kind code	B1
Filing date	Sep 12, 2016
Priority date	Sep 12, 2016
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A method of forming a semiconductor device and resulting structures having vertical transistors with different gate lengths are provided. A sacrificial gate is formed over a channel region of a semiconductor fin. The sacrificial gate includes a first material. The first material in a first portion of the sacrificial gate adjacent to the semiconductor fin is converted to a second material, the first portion having a first depth. The first portion of the sacrificial gate is then removed.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a sacrificial gate over a channel region of a semiconductor fin, the sacrificial gate comprising a first material;
converting the first material in a first portion of the sacrificial gate adjacent to the semiconductor fin to a second material, the first portion having a first depth; and
removing the first portion of the sacrificial gate.

2. The method of claim 1 , further comprising:
implanting arsenic into the first portion of the sacrificial gate to the first depth;
wherein the first material is amorphous silicon;
wherein the second material is arsenic doped silicon.

3. The method of claim 2 , wherein implanting arsenic further comprises an arsenic ion implantation dose of about 1.00×10 15 ions/cm −2 to about 2.00×10 16 ions/cm −2 .

4. The method of claim 2 , wherein implanting arsenic further comprises an arsenic ion implantation dose having a first implant energy selected to achieve the first depth.

5. The method of claim 1 , wherein the first depth is about 10 nm to about 40 nm.

6. The method of claim 1 , further comprising:
forming the sacrificial gate over a channel region of a second semiconductor fin;
converting the first material in a second portion of the sacrificial gate adjacent to the second semiconductor fin to the second material, the second portion having a second depth; and
removing the second portion of the sacrificial gate;
wherein the first depth is different than the second depth.

7. The method of claim 6 , wherein the first depth is about 10 nm and the second depth is about 40 nm.

8. The method of claim 6 , wherein the difference between the first depth and the second depth is about 10 nm to about 40 nm.

9. The method of claim 1 , further comprising:
implanting germanium into the first portion of the sacrificial gate to the first depth;
wherein the first material is amorphous silicon;
wherein the second material is germanium doped silicon.

10. The method of claim 9 , wherein implanting germanium further comprises a germanium ion implantation dose of about 1.00×10 16 ions/cm −2 to about 2.00×10 17 ions/cm −2 .

11. A method for forming a semiconductor device, the method comprising:
forming a sacrificial gate over a channel region of a first semiconductor fin and a channel region of a second semiconductor fin, the sacrificial gate comprising a first material;
converting the first material in a first portion of the sacrificial gate adjacent to the first semiconductor fin to a second material, the first portion having a first depth;
converting the first material in a second portion of the sacrificial gate adjacent to the second semiconductor fin to the second material, the second portion having a second depth; and
removing the first portion and the second portion of the sacrificial gate;
wherein the first depth and the second depth are different.

12. The method of claim 11 , further comprising:
implanting arsenic into the first portion of the sacrificial gate to the first depth; and
implanting arsenic into the second portion of the sacrificial gate to the second depth;
wherein the first material is amorphous silicon;
wherein the second material is arsenic doped silicon.

13. The method of claim 12 , wherein implanting arsenic further comprises an arsenic ion implantation dose of about 1.00×10 15 ions/cm −2 to about 2.00×10 16 ions/cm −2 .

14. The method of claim 12 , wherein implanting arsenic into the first portion of the sacrificial gate to the first depth further comprises an arsenic ion implantation dose having a first implant energy selected to achieve the first depth; and wherein implanting arsenic into the second portion of the sacrificial gate to the second depth further comprises an arsenic ion implantation dose having a second implant energy selected to achieve the second depth.

15. The method of claim 11 , wherein the difference between the first depth and the second depth is about 10 nm to about 40 nm.

16. The method of claim 11 , further comprising:
implanting germanium into the first portion of the sacrificial gate to the first depth; and
implanting germanium into the second portion of the sacrificial gate to the second depth;
wherein the first material is amorphous silicon;
wherein the second material is germanium doped silicon.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Hashemi Pouya
• Ning Tak H
• Reznicek Alexander

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title