Semiconductor package

Patent metadata

Field	Value
Publication number	US-2020020606-A1
Application number	US-201816223642-A
Country	US
Kind code	A1
Filing date	Dec 18, 2018
Priority date	Jul 11, 2018
Publication date	Jan 16, 2020
Grant date	—

Abstract

Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first segment between the first and second semiconductor structures and a second segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second segment.

First claim

1 . A semiconductor package, comprising:
a first substrate; a first semiconductor structure mounted on the first substrate, the first semiconductor structure including a first sidewall and a second sidewall opposite to the first sidewall; a second semiconductor structure mounted on the first substrate and spaced apart from the first semiconductor structure, the second semiconductor structure being adjacent to the first sidewall of the first semiconductor structure; a heat sink covering at least portions of the first semiconductor structure, the second semiconductor structure, and the first substrate; and a thermal interface material layer between the first semiconductor structure and the heat sink and between the second semiconductor structure and the heat sink, the thermal interface material layer including a first thermal interface material segment between the first and second semiconductor structures and a second thermal interface material segment that protrudes beyond the second sidewall, a first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first thermal interface material segment being less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second thermal interface material segment.

2 . The semiconductor package of claim 1 , further comprising:
a first under-fill layer between the first substrate and the first semiconductor structure, wherein the first under-fill layer includes a first under-fill protrusion that protrudes beyond the first sidewall, and wherein the first thermal interface material segment is spaced apart from the first under-fill protrusion.

3 . The semiconductor package of claim 2 , wherein a third distance from the top surface of the first substrate to a highest point of an upper surface of the first under-fill protrusion is equal to or less than about 50% of a fourth distance from the top surface of the first substrate to a top surface of the first semiconductor structure.

4 . The semiconductor package of claim 2 , wherein
the second semiconductor structure includes,
a third sidewall adjacent to the first semiconductor structure, and
a fourth sidewall opposite to the third sidewall,
the thermal interface material layer further includes a third thermal interface material segment that protrudes beyond the fourth sidewall, and a fifth distance from the top surface of the first substrate to a lowest point of a bottom surface of the third thermal interface material segment is greater than the first distance.

5 . The semiconductor package of claim 4 , further comprising:
a second under-fill layer between the first substrate and the second semiconductor structure, wherein the second under-fill layer includes a second under-fill protrusion that protrudes beyond the third sidewall, and wherein the first thermal interface material segment is spaced apart from the second under-fill protrusion.

6 . The semiconductor package of claim 5 , wherein the second under-fill protrusion is in contact with the first under-fill protrusion.

7 . The semiconductor package of claim 5 , wherein a sixth distance from the top surface of the first substrate to a highest point of an upper surface of the second under-fill protrusion is equal to or less than about 50% of a seventh distance from the top surface of the first substrate to a top surface of the second semiconductor structure.

8 . The semiconductor package of claim 5 , wherein
the first and second semiconductor structures defines a gap region therebetween, an upper end of the gap region corresponds to a lower one from among heights of top surfaces of the first and second semiconductor structures, a lower end of the gap region corresponds to the top surface of the first substrate, a first side of the gap region corresponds to the first sidewall, a second side of the gap region, which is opposite to the first side of the gap region, corresponds to the third sidewall, and a sum of volumes of the first thermal interface material segment, the first under-fill protrusion, and the second under-fill protrusion that are positioned in the gap region is equal to or less than about 90% of a total volume of the gap region.

9 . The semiconductor package of claim 8 , wherein
the gap region includes an empty space that is not occupied by the first thermal interface material segment, the first under-fill protrusion, and the second under-fill protrusion, and a volume of the empty space is equal to or greater than about 10% of the total volume of the gap region.

10 . The semiconductor package of claim 1 , further comprising:
a second substrate under the first substrate, wherein the heat sink is attached to the second substrate.

11 . The semiconductor package of claim 10 , further comprising:
an adhesive layer between the heat sink and the second substrate, wherein the adhesive layer includes a same material as the thermal interface material layer.

12 . The semiconductor package of claim 1 , wherein each of the first and second semiconductor structures is one of a semiconductor chip or a sub-semiconductor package.

13 . The semiconductor package of claim 1 , wherein a cross-section of the first thermal interface material segment has a profile having an inflection point at a lower surface thereof.

14 . The semiconductor package of claim 13 , wherein:
a top surface of the first semiconductor structure is lower than a top surface of the second semiconductor structure, and the inflection point is nearer to the first semiconductor structure than to the second semiconductor structure.

15 . The semiconductor package of claim 1 , wherein one of the first semiconductor structure or the second semiconductor structure includes a sub-package substrate and at least one semiconductor chip mounted on the sub-package substrate,
wherein the thermal interface material layer is in contact with a top surface of the semiconductor chip.

16 . A semiconductor package, comprising:
a first substrate; a first semiconductor structure mounted on the first substrate, the first semiconductor structure including a first sidewall and a second sidewall opposite to the first sidewall; a second semiconductor structure mounted on the first substrate and spaced apart from the first semiconductor structure, the second semiconductor structure being adjacent to the first sidewall of the first semiconductor structure; a heat sink covering at least portions of the first semiconductor structure, the second semiconductor structure, and the first substrate; and a thermal interface material layer between the first semiconductor structure and the heat sink and between the second semiconductor structure and the heat sink, the thermal interface material layer including a first thermal interface material segment adjacent to the first sidewall and a second thermal interface material segment adjacent to the second sidewall, the first thermal interface material segment being thicker than the second thermal interface material segment.

17 . The semiconductor package of claim 16 , further comprising:
a first under-fill layer between the first substrate and the first semiconductor structure, the first under-fill layer including a first under-fill protrusion that protrudes beyond the first sidewall, wherein the first thermal interface material segment is spaced apart from the first under-fill protrusion.

18 . The semiconductor package of claim 17 , further comprising:
a second under-fill layer be

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hee-Jeong
• Lyu Juhyun
• Kang Un-Byoung
• Lee Jongho

Classifications

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title