Semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-2020006384-A1
Application number	US-201916565765-A
Country	US
Kind code	A1
Filing date	Sep 10, 2019
Priority date	Jun 7, 2005
Publication date	Jan 2, 2020
Grant date	—

Abstract

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

First claim

1 - 4 . (canceled)

5 . A semiconductor integrated circuit device formed on one chip comprising:
a first functional block connected to a first power supply line and a second power supply line; a second functional block connected to the first power supply line and a third power supply line and communicating with the first functional block; a third functional block connected to the first power supply line and a fourth power supply line and communicating with the first functional block; a first power switch shutting down the first functional block from power supply via the second power supply line; a second power switch shutting down the second functional block from power supply via the third power supply line; and a third power switch shutting down the third functional block from power supply via the fourth power supply line, wherein the first functional block is shut down by the first power switch when the second and the third functional blocks are shut down.

6 . A semiconductor integrated circuit device according to claim 5 ,
wherein the first functional block is laid out inside each of the second and third functional blocks.

7 . A semiconductor integrated circuit device according to claim 6 ,
wherein the first power switch to shut down the first functional block in the second functional block and the first power switch to shut down the first functional block in the third functional block are provided independently.

8 . A semiconductor integrated circuit device according to claim 7 , further comprising:
a first power switch controller that controls the first power switch to shut down the first functional block in the second functional block; and a second power switch controller that controls the first power switch to shut down the first functional block in the third functional block.

9 . A semiconductor integrated circuit device according to claim 6 ,
wherein the first power switch to shut down the first functional block in the second functional block is provided in common with the first power switch to shut down the first functional block in the third functional block.

10 . A semiconductor integrated circuit device according to claim 9 , further comprising a power switch controller,
wherein the power switch controller controls the first power switch.

11 . A semiconductor integrated circuit device according to claim 8 ,
wherein a first voltage is supplied to the first power supply line and a second voltage is supplied to the second to fourth power supply lines.

12 . A semiconductor integrated circuit device according to claim 11 ,
wherein the first voltage is higher than the second voltage.

13 . A semiconductor integrated circuit device according to claim 5 , further comprising a fourth functional block connected to the first power supply line and a fifth power supply line,
wherein the fourth functional block is not shut down, and wherein the fourth functional block comprises a power switch controller that controls the first to third power switches.

14 . A semiconductor integrated circuit device according to claim 8 ,
wherein each of the first to third functional blocks comprises a first MISFET, wherein each of the first to third power switches and the first and the second power switch controllers comprises a second MISFET having larger gate insulation film thickness than the first MISFET, wherein each of the first to third power switches further comprises a first switch and a second switch, and wherein the first and second power switch controllers turn the first switch on first and turn the second switch on second, respectively.

15 . A semiconductor integrated circuit device according to claim 9 , further comprising a power switch controller,
wherein each of the first to third functional blocks comprises a first MISFET, wherein each of the first to third power switches and the power switch controller comprises a second MISFET having larger gate insulation film thickness than the first MISFET, wherein each of the first to third power switches further comprise a first switch and a second switch, and wherein the power switch controller turns the first switch on first and turns the second switch on second.

16 . A semiconductor integrated circuit device according to claim 14 ,
wherein each of the first and second power switch controllers comprise:
means to detect whether a voltage of a virtual power supply line reaches a voltage level in which the corresponding functional block can operate; and
a sensor circuit to detect the voltage of the virtual power supply, and
wherein the first and second power switch controllers control the first and the second switches, respectively.

17 . A semiconductor integrated circuit device according to claim 15 ,
wherein the power switch controller comprises:
means to detect whether a voltage of a virtual power supply line reaches a voltage level in which the first functional block can operate; and
a sensor circuit to detect the voltage of the virtual power supply, and
wherein the power switch controller controls both the first and the second switches.

18 . A semiconductor integrated circuit device according to claim 14 ,
wherein each of the first and second power switch controllers further comprises a sensor circuit that detects a voltage of a gate of the second MISFET to control each of the first and second switches, and wherein each of the first and second power switch controllers compares the voltage of the gate of the second MISFET with a predetermined voltage level, and determines whether each of the first and second switches is on or not.

19 . A semiconductor integrated circuit device according to claim 15 ,
wherein the power switch controller further comprises a sensor circuit that detects a voltage of a gate of the second MISFET to control each of the first and second switches, and wherein the power switch controller compares the voltage of the gate of the second MISFET with a predetermined voltage level, and determines whether each of the first and the second switches is on or not.

20 . A semiconductor integrated circuit device according to claim 16 ,
wherein each of the first and second power switch controllers further comprises a clock generator, and wherein the sensor circuit includes a dynamic comparator that detects the voltage synchronized with a clock signal generated by the clock generator.

21 . A semiconductor integrated circuit device according to claim 17 ,
wherein the power switch controller further comprises a clock generator, and wherein the sensor circuit includes a dynamic comparator that detects the voltage synchronized with a clock signal generated by the clock generator.

Assignees

• Renesas Electronics Corp

Inventors

• Kanno Yusuke
• Mizuno Hiroyuki
• Yasu Yoshihiko
• Hirose Kenji
• Irita Takahiro

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H03K19/00346

  Modifications for eliminating interference or parasitic voltages or currents · CPC title

• H03K19/0008

  Arrangements for reducing power consumption · CPC title

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title