Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016379992-A1
Application number	US-201415039725-A
Country	US
Kind code	A1
Filing date	Nov 26, 2014
Priority date	Nov 28, 2013
Publication date	Dec 29, 2016
Grant date	—

Abstract

A semiconductor device ( 1 ) is manufactured which includes a SiC epitaxial layer ( 28 ), a plurality of transistor cells ( 18 ) that are formed in the SiC epitaxial layer ( 28 ) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode ( 19 ) that faces a channel region ( 32 ) of the transistor cells ( 18 ) in which a channel is formed when the semiconductor device ( 1 ) is in an ON state, a gate metal ( 44 ) that is exposed at the topmost surface for electrical connection with the outside: and that is electrically connected to the gate electrode ( 19 ) while being physically separated from the gate electrode ( 19 ), and a built-in resistor ( 21 ) that is made of polysilicon and that is disposed below the gate metal ( 41 ) so as to electrically connect the gate metal ( 44 ) and the gate electrode ( 19 ) together.

First claim

1 . A semiconductor device comprising: a SiC semiconductor layer;
a plurality of cells that are formed in the SiC semiconductor layer and that are subjected to ON/OFF control by means of a predetermined control voltage; a control electrode that faces a channel region of the cells in which a channel is formed when turned on; a control pad that is exposed at a topmost surface for electric connection with an outside, the control pad being physically separated from the control electrode and being electrically connected to the control electrode; and a built-in resistor that is disposed below the control pad and that is made of polysilicon, the built-in resistor electrically connecting the control pad and the control electrode together.

2 . The semiconductor device according to claim 1 , wherein the control pad is formed independently while a periphery of the control pad is surrounded by a space, and
the built-in resistor is disposed in a region below the control pad with an interlayer film between the built-in resistor and the control pad.

3 . The semiconductor device according to claim 2 , wherein the built-in resistor is selectively disposed in a region below the control pad, and
the interlayer film is buried in a first region in which the built-in resistor is not disposed, the first region being included in the region below the control pad.

4 . The semiconductor device according to claim 3 , further comprising an insulating film disposed between the built-in resistor and the SiC semiconductor layer,
wherein a film made of an extension portion of the insulating film is disposed between the interlayer film and the SiC semiconductor layer in the first region.

5 . The semiconductor device according to claim 4 , wherein, in the SiC semiconductor layer, an impurity region that has a concentration of 1×10 19 cm −3 or less is selectively formed in a region facing the built-in resistor with the insulating film between the region and the built-in resistor.

6 . The semiconductor device according to claim 2 , wherein a wire region to which a bonding wire is connected is selectively formed on a surface of the control pad, and
the built-in resistor is selectively disposed in a region that avoids the wire region when planarly viewed from a normal direction of the SiC semiconductor layer.

7 . The semiconductor device according to claim 6 , wherein the built-in resistor is disposed below a peripheral edge of the control pad, and the wire region is formed at a middle of the control pad surrounded by the peripheral edge.

8 . The semiconductor device according to claim 2 , further comprising a contact via that passes through the interlayer film and by which the control pad and the built-in resistor are electrically connected together.

9 . The semiconductor device according to claim 1 , wherein a plurality of the built-in resistors are arranged so as to be symmetrical to each other when planarly viewed from the normal direction of the SiC semiconductor layer.

10 . The semiconductor device according to claim 1 , wherein the control electrode is made of p type polysilicon.

11 . The semiconductor device according to claim 10 , wherein the control electrode includes B (boron) serving as a p type impurity.

12 . The semiconductor device according to claim 1 , wherein a resistance value of the built-in resistor is 2 Ω to 40 Ω.

13 . The semiconductor device according to claim 1 , wherein a resistance value obtained by totalizing the resistance value of the control electrode and the resistance value of the built-in resistor is 4 Ω to 50 Ω.

14 . The semiconductor device according to claim 1 , wherein sheet resistance of the built-in resistor is 10 Ω/□ or more.

15 . The semiconductor device according to claim 1 , wherein a size of the built-in resistor is 200 μm□ or less for every built-in resistor when planarly viewed from the normal direction of the SiC semiconductor layer.

16 . The semiconductor device according to claim 1 , wherein the built-in resistor is 200 μm or less in thickness.

17 . The semiconductor device according to claim 1 , further comprising a finger that is disposed on a topmost surface of the semiconductor device in the same way as the control pad and that extends from the control pad so as to partition a predetermined region,
wherein the plurality of cells are arranged in a region partitioned by the finger, and the built-in resistor connects the control pad and the finger together.

18 . The semiconductor device according to claim 17 , wherein the finger is made of a metal wiring.

19 . The semiconductor device according to claim 18 , wherein the metal wiring is made of Al.

20 . The semiconductor device according to claim 18 , wherein the metal wiring is made of AlCu.

21 . The semiconductor device according to claim 18 , wherein the metal wiring is made of Cu.

22 . The semiconductor device according to claim 1 , wherein the cell forms a MOSFET cell, and
the control pad includes a gate pad to apply a gate voltage to the MOSFET cell.

23 . The semiconductor device according to claim 22 , wherein the MOSFET cell includes a planar gate structure.

24 . The semiconductor device according to claim 22 , wherein the MOSFET cell includes a trench gate structure.

25 . The semiconductor device according to claim 1 , wherein the cell forms an IGBT cell, and
the control pad includes a gate pad to apply a gate voltage to the IGBT cell,

26 . A semiconductor device comprising:
a SiC semiconductor layer; a control pad exposed at a topmost surface for electric connection with an outside; a finger that extends from the control pad so as to partition a predetermined region and that is electrically connected to the control pad; a plurality of cells that are arranged in a region partitioned by the finger in the SiC semiconductor layer and that are subjected to ON/OFF control by means of a control voltage from the control pad; a control electrode that faces a channel region of the cells in which a channel is formed when turned on; and a built-in resistor that is disposed below the control pad and the finger and that connects the control pad and the finger together, the built-in resistor being made of a material that has a resistance value that is equal to or larger than the finger.

27 . The semiconductor device according to claim 26 , wherein the built-in resistor is made of a metal.

28 . A semiconductor device comprising:
a SiC semiconductor layer; a plurality of cells that are formed in the SiC semiconductor layer and that are subjected to ON/OFF control by means of a predetermined control voltage; a control electrode that faces a channel region of the cells in which a channel is formed when turned on; a control pad that is exposed at a topmost surface for electric connection with an outside, the control pad being physically separated from the control electrode and being electrically connected to the control electrode; and a built-in resistor that is made of polysilicon, the built-in resistor electrically connecting the control pad and the control electrode together.

Assignees

• Rohm Co Ltd

Inventors

• Nagao Katsuhisa
• Kawamoto Noriaki

Classifications

• H10W20/4424

  Copper alloys · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/4407

  Aluminium alloys · CPC title

• H10W20/4405

  the principal metal being aluminium · CPC title

• H10W20/43

  Layouts of interconnections · CPC title