Semiconductor chip and stack type semiconductor apparatus using the same

Patent metadata

Field	Value
Publication number	US-9466555-B2
Application number	US-201514624720-A
Country	US
Kind code	B2
Filing date	Feb 18, 2015
Priority date	Dec 5, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may include a through via configured for signal transfer with another semiconductor chip. The semiconductor may include an internal information processing circuit configured to transmit internal information selected from the internal information to the through via, or may be configured to output internal information of the other semiconductor chip, which has been transmitted through the through via, to an exterior through a special purpose pin, in response to test signals.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a core block configured to store and output data, and configured to output internal information;
a through via configured for signal transfer with another semiconductor chip;
an internal information processing circuit configured to transmit internal information selected from the internal information to the through via, or configured to output internal information of the other semiconductor chip transmitted through the through via, to an exterior through a special purpose pin, in response to test signals; and
input/output pads configured for inputting and outputting data between the core block and an exterior of the semiconductor chip.

2. The semiconductor chip according to claim 1 , wherein the special purpose pin is configured to provide a parity of a command, an address, or an abnormal operation state of the semiconductor chip exterior to the semiconductor chip and other semiconductor chip.

3. The semiconductor chip according to claim 1 , wherein the internal information is used in the semiconductor chip, and includes signals which cannot be outputted through the input/output pads of the semiconductor chip.

4. The semiconductor chip according to claim 1 , wherein the internal information that is outputted through the input/output pads of the semiconductor chip are internal signals passing through internal circuits according to an external command.

5. The semiconductor chip according to claim 4 , wherein the internal information includes read command-based signal and write command-based signals.

6. The semiconductor chip according to claim 1 , wherein the internal information processing circuit comprises:
a multiplexer configured to select and output one of the internal information according to a first test signal of the test signals;
a transmitter configured to be activated according to a second test signal of the test signals and to transmit an output signal of the multiplexer to the through via;
a receiver configured to be activated according to a third test signal of the test signals and to receive and output the internal information of the other semiconductor chip transmitted through the through via; and
a driver configured to be activated according to the third test signal, and to output an output signal of the receiver through the special purpose pin.

7. The semiconductor chip according to claim 6 ,
wherein an input terminal of the multiplexer is coupled to internal circuit configurations of the core block,
wherein the internal information is used in the internal circuit configurations of the core block.

8. The semiconductor chip according to claim 1 , wherein the semiconductor chip is a master chip and the another semiconductor chip is a slave chip and are coupled to each other by trough-silicon vias.

9. A stack type semiconductor apparatus comprising:
a plurality of stacked semiconductor chips,
wherein a special purpose pin is coupled to any one of the plurality of semiconductor chips, and internal information of any one semiconductor chip selected from among the plurality of semiconductor chips is outputted to an exterior through the special purpose pin,
wherein one or more of the plurality of semiconductor chips comprises:
input/output pads configured for inputting and outputting data to and from an exterior of the semiconductor apparatus.

10. The stack type semiconductor apparatus according to claim 9 , wherein the plurality of semiconductor chips are configured to transmit a signal through a through via, the internal information of the selected semiconductor chip is transmitted to the through via, and the semiconductor chip coupled to the special purpose pin outputs the internal information received through the through via to an exterior of the semiconductor apparatus through the special purpose pin.

11. The stack type semiconductor apparatus according to claim 9 , wherein the semiconductor chip coupled to the special purpose pin is a master chip and semiconductor chips, except for the semiconductor chip coupled to the special purpose pin, are slave chips.

12. The stack type semiconductor apparatus according to claim 9 , wherein the special purpose pin is configured to provide a parity of a command, an address, or an abnormal operation state of the semiconductor chip exterior to the semiconductor apparatus.

13. The stack type semiconductor apparatus according to claim 9 , wherein the internal information represents signals used in each of the plurality of semiconductor chips, and includes signals which cannot be outputted through the input/output pads of the semiconductor chip.

14. The stack type semiconductor apparatus according to claim 9 , wherein the internal information that is outputted through the input/output pads of the semiconductor chip are internal signals passing through internal circuits according to an external command.

15. The stack type semiconductor apparatus according to claim 14 , wherein the internal information includes read command-based signal and write command-based signals.

16. The stack type semiconductor apparatus according to claim 9 , wherein each of the plurality of semiconductor chips comprises:
a core block configured to store and output data, and configured to output internal information;
a through via configured for signal transfer with another semiconductor chip; and
an internal information processing circuit configured to transmit the internal information to the through via, or configured to output internal information of the other semiconductor chip, which has been transmitted through the through via, to an exterior through the special purpose pin, in response to test signals.

17. The stack type semiconductor apparatus according to claim 16 , wherein the internal information processing circuit comprises:
a multiplexer configured to select and output one of the internal information according to a first test signal of the test signals;
a transmitter configured to be activated according to a second test signal of the test signals and to transmit an output signal of the multiplexer to the through via;
a receiver configured to be activated according to a third test signal of the test signals and to receive and output the internal information of the other semiconductor chip, which has been transmitted through the through via; and
a driver configured to be activated according to the third test signal, and to output an output signal of the receiver through the special purpose pin.

18. The stack type semiconductor apparatus according to claim 17 ,
wherein an input terminal of the multiplexer is coupled to internal circuit configurations of the core block,
wherein the internal information is used in the internal circuit configurations of the core block.

Assignees

• Sk Hynix Inc

Inventors

• Lee Jae Seung
• Yoon Byung Kuk

Classifications

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/08

  Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title