Integrated circuit package substrate

Patent metadata

Field	Value
Publication number	US-2019304892-A1
Application number	US-201916381889-A
Country	US
Kind code	A1
Filing date	Apr 11, 2019
Priority date	Oct 16, 2013
Publication date	Oct 3, 2019
Grant date	—

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

First claim

1 . (canceled)

2 . A method for providing a package substrate, comprising:
providing one or more lands on a first side of the package substrate, the package substrate including a second side opposite the first side; disposing one or more die bond pads on the second side, including providing the one or more die bond pads in a die interconnect region of the package substrate, wherein the die interconnect region comprises a silicon bridge; depositing a first surface finish on at least one of the one or more lands; and depositing a second surface finish on at least one of the die bond pads; wherein the second surface finish has a different chemical composition than the first surface finish.

3 . The method of claim 2 , wherein disposing the die bond pads includes disposing at least one die bond pad on the silicon bridge.

4 . The method of claim 2 , wherein the first surface finish is an outermost surface finish on the one or more lands and the second surface finish is an outermost surface finish on the one or more die bond pads features.

5 . The method of claim 2 , wherein the second surface finish is imidazole or an imidazole derivative.

6 . The method of claim 2 , wherein the second surface finish is gold (Au).

7 . The method of claim 2 , wherein the second surface finish is a combination of palladium (Pd) and gold (Au).

8 . The method of claim 2 , wherein the second surface finish has a thickness of less than or equal to 500 nanometers.

9 . The method of claim 2 , wherein the first surface finish comprises nickel (Ni).

10 . The method of claim 9 , wherein the first surface finish further comprises one or both of palladium (Pd) or gold (Au).

11 . A method for providing an assembly, comprising:
disposing a silicon bridge in a substrate of the assembly; disposing a plurality of lands on a first side of the substrate; providing a plurality of die bond pads, including disposing at least one die bond pad on the silicon bridge and disposing at least one other die bond pad on a second side of the substrate, the second side of the substrate opposite the first side; depositing a first surface finish on at least one of the lands; depositing a second surface finish on at least one of the die bond pads, wherein the second surface finish has a different chemical composition than the first surface finish; extending a first set of interconnect structures between a first die of the assembly and the die bond pads; and extending a second set of interconnect structures between a second die of the assembly and the die bond pads.

12 . The method of claim 11 , further comprising:
disposing routing features in the silicon bridge, to electrically couple the first die and the second die.

13 . The method of claim 12 , further comprising:
disposing routing features in the substrate, to electrically couple the first die and the second die.

14 . The method of claim 11 , wherein the first surface finish is an outermost surface finish on the one or more lands and the second surface finish is an outermost surface finish on the one or more die bond pads features.

15 . The method of claim 11 , wherein the second surface finish is imidazole or an imidazole derivative.

16 . The method of claim 11 , wherein the second surface finish is gold (Au).

17 . The method of claim 11 , wherein the second surface finish is a combination of palladium (Pd) and gold (Au).

18 . The method of claim 11 , wherein the second surface finish has a thickness of less than or equal to 500 nanometers.

19 . The method of claim 11 , wherein the first surface finish comprises nickel (Ni).

20 . The method of claim 19 , wherein the first surface finish further comprises one or both of palladium (Pd) or gold (Au).

21 . The method of claim 11 , wherein the first and second dies comprise integrated circuits (IC).

Assignees

• Intel Corp

Inventors

• Zhang Qinglei
• Lotz Stefanie M

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title