High voltage resistor with high voltage junction termination
US-2024014260-A1 · Jan 11, 2024 · US
US2019252504A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2019252504-A1 |
| Application number | US-201716333269-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 25, 2017 |
| Priority date | Sep 26, 2016 |
| Publication date | Aug 15, 2019 |
| Grant date | — |
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An n-type SiC single crystal substrate of the present invention is provided which is a substrate doped with both a donor and an acceptor, and has a difference between a donor concentration and an acceptor concentration in an outer peripheral portion which is smaller than a difference between a donor concentration and an acceptor concentration in a central portion, and is smaller than 3.0×10 19 /cm 3 .
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1 . An n-type SiC single crystal substrate which is doped with both a donor and an acceptor, wherein a difference between a donor concentration and an acceptor concentration in an outer peripheral portion of the substrate is smaller than a difference between a donor concentration and an acceptor concentration in a central portion, and the difference between the donor concentration and the acceptor concentration in said outer peripheral portion is smaller than 3.0×10 19 /cm 3 . 2 . The n-type SiC single crystal substrate according to claim 1 , wherein the difference between the donor concentration and the acceptor concentration in the outer peripheral portion is smaller than 2.0×10 19 /cm 3 . 3 . The n-type SiC single crystal substrate according to claim 1 , wherein the difference between the donor concentration and the acceptor concentration in the central portion is larger than the difference between the donor concentration and the acceptor concentration in the outer peripheral portion by more than 1.0×10 19 /cm 3 . 4 . A SiC epitaxial wafer having a SiC epitaxial film formed on the n-type SiC single crystal substrate according to claim 1 . 5 . The epitaxial wafer according to claim 4 , wherein a stacking fault density of said n-type SiC single crystal substrate is 5 cm −1 or less. 6 . A method for producing an n-type SiC single crystal substrate, the method comprising: a crystal growth step of laminating a SiC single crystal while co-doping a donor and an acceptor on one surface of a seed crystal by a sublimation recrystallization method, wherein a crystal growth surface is maintained in a convex shape in at least a part of said crystal growth step. 7 . The method for producing an n-type SiC single crystal substrate according to claim 6 , wherein a thermal loading step at 1,000° C. or higher and 2,000° C. or lower is performed on said laminated SiC single crystal after said crystal growth step. 8 . The method for producing an n-type SiC single crystal substrate according to claim 6 , wherein said crystal growth step is a step for producing a SiC single crystal ingot, and comprises: a step of slicing a substrate from said SiC single crystal ingot; a step of performing a beveling process on an outer peripheral portion of the sliced substrate, and a step of performing a heat treatment at 1,000° C. or higher and 2,000° C. or lower after performing the beveling process. 9 . The method for producing an n-type SiC single crystal substrate according to claim 6 , wherein in said crystal growth step, crystal growth is performed in an environment in which a temperature in a central portion of the seed crystal is lower than that in an outer peripheral portion of the seed crystal to maintain the crystal growth surface in a convex shape. 10 . The method for producing an n-type SiC single crystal substrate according to claim 6 , wherein in said crystal growth step, crystal growth is performed in an environment in which a temperature in a central portion of the seed crystal is lower than that in an outer peripheral portion of the seed crystal.
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