Pin modification for standard cells

Patent metadata

Field	Value
Publication number	US-2019103392-A1
Application number	US-201815966507-A
Country	US
Kind code	A1
Filing date	Apr 30, 2018
Priority date	Sep 29, 2017
Publication date	Apr 4, 2019
Grant date	—

Abstract

The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a wire cut between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the wire cut separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

First claim

What is claimed is:

1 . A method for routing a standard cell with a plurality of pins, the method comprising:
modifying a dimension of at least one pin from the plurality of pins, wherein the at least one pin is spaced at an increased distance from a boundary of the standard cell than an original position of the at least one pin; routing an interconnect from the at least one pin to a via placed on a pin track located between the at least one pin and the boundary; and inserting a wire cut between the interconnect and at least one pin from an adjacent standard cell, wherein the wire cut separates the interconnect from the at least one pin of the adjacent standard cell by at least a predetermined distance, and wherein at least one of the modifying, routing, and inserting is performed by a processor.

2 . The method of claim 1 ,
wherein the standard cell comprises at least one pin in an upper portion of the standard cell, at least one pin in a middle portion of the standard cell, and at least one pin in a lower portion of the standard cell; and wherein the at least one pin in the middle portion of the standard cell comprises the at least one pin spaced at the increased distance from the boundary of the standard cell than the original position of the at least one pin.

3 . The method of claim 2 , wherein the at least one pin in the upper portion of the standard cell and the at least one pin in the lower portion of the standard cell are spaced closer to the boundary of the standard cell than the at least one pin in the middle portion of the standard cell.

4 . The method of claim 1 , wherein modifying the dimension of the at least one pin comprises modifying a dimension of an other pin from the plurality of pins, wherein the other pin is spaced at the same distance from the boundary of the standard cell as the at least one pin.

5 . The method of claim 1 , wherein modifying the dimension of the at least on pin comprises spacing the at least one pin at a minimum distance from the boundary of the standard cell, and wherein the minimum distance is based on (i) a width dimension of the wire cut, (ii) one-half of a width dimension of the via, and (iii) a minimum distance requirement between the interconnect and the via.

6 . The method of claim 1 , wherein routing the interconnect comprises routing the interconnect from the at least one pin to the via placed on the pin track, the pin track located on the boundary of the standard cell.

7 . The method of claim 1 , wherein routing the interconnect comprises routing the interconnect from the at least one pin to the via placed on the pin track, the pin track located outside of the standard cell.

8 . The method of claim 1 , wherein in response to the separation between the interconnect and the at least one pin of the adjacent standard cell being less than the predetermined distance, the method further comprises re-modifying the dimension of the at least one pin from the plurality of pins, re-routing the interconnect, or a combination thereof.

9 . A computer system comprising:
a memory configured to store instructions; and a processor, that when executing the instructions, is configured to perform operations for routing a standard cell with a plurality of pins, the operations comprising:
modifying a dimension of at least one pin from the plurality of pins, wherein the at least one pin is spaced at an increased distance from a boundary of the standard cell than an original position of the at least one pin;
routing an interconnect from the at least one pin to a via placed on a pin track located between the at least one pin and the boundary;
inserting a wire cut between the interconnect and at least one pin from an adjacent standard cell; and
verifying the wire cut separates the interconnect from the at least one pin of the adjacent standard cell by at least a predetermined distance.

10 . The computer system of claim 9 , wherein modifying the dimension of the at least one pin comprises modifying a dimension of an other pin from the plurality of pins, wherein the other pin is spaced at the same distance from the boundary of the standard cell as the at least one pin.

11 . The computer system of claim 9 , wherein modifying the dimension of the at least on pin comprises spacing the at least one pin at a minimum distance from the boundary of the standard cell, and wherein the minimum distance is based on (i) a width dimension of the wire cut, (ii) one-half of a width dimension of the via, and (iii) a minimum distance requirement between the interconnect and the via.

12 . The computer system of claim 9 , wherein routing the interconnect comprises routing the interconnect from the at least one pin to the via placed on the pin track, the pin track located on the boundary of the standard cell.

13 . The computer system of claim 9 , wherein routing the interconnect comprises routing the interconnect from the at least one pin to the via placed on the pin track, the pin track located outside of the standard cell.

14 . The computer system of claim 9 , wherein in response to the separation between the interconnect and the at least one pin of the adjacent standard cell being less than the predetermined distance, the method further comprises re-modifying the dimension of the at least one pin from the plurality of pins, re-routing the interconnect, or a combination thereof.

15 . A non-transitory computer-readable medium having instructions stored thereon that, when executed by a computing device, causes the computing device to perform operations comprising:
modifying a dimension of at least one pin from the plurality of pins, wherein the at least one pin is spaced at an increased distance from a boundary of the standard cell than an original position of the at least one pin; routing an interconnect from the at least one pin to a via placed on a pin track located between the at least one pin and the boundary; inserting a wire cut between the interconnect and at least one pin from an adjacent standard cell; and verifying the wire cut separates the interconnect from the at least one pin of the adjacent standard cell by at least a predetermined distance.

16 . The non-transitory computer-readable medium of claim 15 , wherein modifying the dimension of the at least one pin comprises modifying a dimension of an other pin from the plurality of pins, wherein the other pin is spaced at the same distance from the boundary of the standard cell as the at least one pin.

17 . The non-transitory computer-readable medium of claim 15 , wherein modifying the dimension of the at least on pin comprises spacing the at least one pin at a minimum distance from the boundary of the standard cell, and wherein the minimum distance is based on (i) a width dimension of the wire cut, (ii) one-half of a width dimension of the via, and (iii) a minimum distance requirement between the interconnect and the via.

18 . The non-transitory computer-readable medium of claim 15 , wherein routing the interconnect comprises routing the interconnect from the at least one pin to the via placed on the pin track, the pin track located on the boundary of the standard cell.

19 . The non-transitory computer-readable medium of claim 15 , wherein routing the interconnect comprises routing the interconnect from the at least one pin to the via placed on the pin track, the pin track located outside of the standard cell.

20 . The non-transitory computer-readable medium of claim 15 , wherein in response to the separation

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Fong-Yuan
• Chen Sheng-Hsiung
• Chiang Ting-Wei
• Lin Chung-Te
• Yang Jung-Chan
• Lu Lee-Chung
• Huang Po-Hsiang
• Chen Chun-Chen

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/11807

  Electricity · mapped topic

• G06F17/5077

  Physics · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic