Integrated circuit, system for and method of forming an integrated circuit

Patent metadata

Field	Value
Publication number	US-10262981-B2
Application number	US-201715465167-A
Country	US
Kind code	B2
Filing date	Mar 21, 2017
Priority date	Apr 29, 2016
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

A method of forming an integrated circuit is disclosed. The method includes generating, by a processor, a layout design of the integrated circuit, outputting the integrated circuit based on the layout design, and removing a portion of a conductive structure of the integrated circuit to form a first conductive structure and a second conductive structure. Generating the layout design includes generating a standard cell layout having a set of conductive feature layout patterns, placing a power layout pattern with the standard cell layout according to at least one design criterion, and extending at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to a boundary of the power layout pattern. The power layout pattern includes a cut feature layout pattern. The cut feature layout pattern identifies a location of the removed portion of the conductive structure of the integrated circuit.

First claim

What is claimed is:

1. A method of forming an integrated circuit, the method comprising:
generating, by a processor, a layout design of the integrated circuit, wherein the generating of the layout design comprises:
generating a standard cell layout having a set of conductive feature layout patterns;
placing a power layout pattern with the standard cell layout according to at least one design criterion, the power layout pattern comprising a cut feature layout pattern; and
extending an endpoint of at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to from a first position spaced from a boundary of the power layout pattern to a second position contacting the boundary of the power layout pattern;

outputting the integrated circuit based on the layout design, the integrated circuit having a conductive structure; and
removing a portion of the conductive structure to form a first conductive structure and a second conductive structure, and the cut feature layout pattern identifying a location of the removed portion of the conductive structure of the integrated circuit,
wherein the layout design of the integrated circuit is provided to a fabrication facility for manufacturing the integrated circuit.

2. The method according to claim 1 , wherein the generating of the layout design of the integrated circuit further comprises:
reducing a size of the set of conductive feature layout patterns of the standard cell.

3. The method according to claim 1 , wherein the generating of the standard cell layout comprises:
retrieving the standard cell layout from a standard cell library, the standard cell library having pre-designed layouts of circuit elements, and
placing the standard cell layout into one or more locations on the layout design of the integrated circuit.

4. The method according to claim 1 , wherein the generating of the layout design of the integrated circuit further comprises:
selecting the power layout pattern from a library, the library having pre-designed layouts of power structures configured to supply a voltage to the integrated circuit.

5. The method according to claim 1 , wherein the at least one design criterion comprises:
the power layout pattern does not overlap the set of conductive feature layout patterns; or
the power layout pattern is separated from the set of conductive feature layout patterns by at least a minimum spacing.

6. The method according to claim 1 , wherein
the set of conductive feature layout patterns comprises a first conductive feature layout pattern extending in a first direction, and
the power layout pattern further comprises a second conductive feature layout pattern extending in the first direction,
the first conductive feature layout pattern and the second conductive feature layout pattern being:
aligned in a second direction different than the first direction; and
separated from each other in the first direction by the cut feature layout pattern.

7. The method according to claim 1 , wherein the removing of the portion of the conductive structure comprises:
performing an etch process on the removed portion of the conductive structure.

8. The method according to claim 1 , wherein
the removed portion of the conductive structure comprises:
a cut width in a first direction, and
a cut length in a second direction that is orthogonal to the first direction;

the cut feature layout pattern comprises:
a pattern width in the first direction, and
a pattern length in the second direction;

the pattern width corresponds to the cut width, the pattern length corresponds to the cut length, and the boundary of the power layout pattern is a boundary of the cut feature layout pattern.

9. The method according to claim 1 , wherein the power layout pattern further comprises:
a first conductive feature layout pattern extending in a first direction;
a second conductive feature layout pattern extending in a second direction that is orthogonal to the first direction;
a first via feature layout pattern between the first conductive feature layout pattern and the second conductive feature layout pattern; and
another cut feature layout pattern extending in the second direction and positioned at a first end of the first conductive feature layout pattern;
wherein the cut feature layout pattern extends in the second direction and is positioned at a second end of the first conductive feature layout pattern opposite to the first end.

10. A system comprising:
a non-transitory computer readable medium configured to store executable instructions; and
a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions to:
generate a standard cell layout having a set of conductive feature layout patterns;
select a power layout pattern from a library, the library having pre-designed layouts of power structures configured to supply a voltage to the integrated circuit, and the power layout pattern comprising a cut feature layout pattern;
place the selected power layout pattern with the standard cell layout according to at least one design criterion; and
extend at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to a boundary of the selected power layout pattern, wherein prior to the extending the at least one conductive feature is separated from the boundary of the selected power layout pattern;

wherein the integrated circuit has a first conductive structure and a second conductive structure separated by a cut region, and the cut feature layout pattern identifies a location of the cut region of the integrated circuit, and
provide the layout design of the integrated circuit to a fabrication facility for manufacturing the integrated circuit.

11. The system of claim 10 , wherein the processor is further configured to execute instructions to reduce a size of the set of conductive feature layout patterns of the standard cell.

12. The system of claim 10 , wherein the processor configured to execute the instructions to generate the standard cell layout comprises the processor being configured to execute instructions to:
retrieve the standard cell layout from a standard cell library, the standard cell library having pre-designed layouts of circuit elements, and
place the standard cell layout into one or more locations on the layout design of the integrated circuit.

13. The system of claim 10 , wherein the at least one design criterion comprises:
the selected power layout pattern does not overlap the set of conductive feature layout patterns; or
the selected power layout pattern is separated from the set of conductive feature layout patterns by at least a minimum spacing.

14. The system of claim 10 , wherein
the set of conductive feature layout patterns comprises a first conductive feature layout pattern extending in a first direction,
the power layout pattern further comprises a second conductive feature layout pattern extending in the first direction, and
the first conductive feature layout pattern and the second conductive feature layout pattern being:
aligned in a second direction different than the first direction; and
separated from each other in the first direction by the cut feature layout pattern.

15. The system of claim 10 , wherein the selected power layout pattern further comprises:
a first conductive feature layout pattern extending in a first direction;
a second conductive feature layout pattern extending in a second direction different than the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Fong-Yuan
• Chang Jyun-Hao
• Chen Sheng-Hsiung
• Huang Po-Hsiang
• YUAN Lipen

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/0207 Primary

  Electricity · mapped topic