Computer implemented system and method for generating a layout of a cell defining a circuit component

Patent metadata

Field	Value
Publication number	US-10083269-B2
Application number	US-201414528314-A
Country	US
Kind code	B2
Filing date	Oct 30, 2014
Priority date	Nov 19, 2013
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

First claim

We claim:

1. A computer implemented method of generating an integrated circuit layout of a cell defining a circuit component, the integrated circuit layout providing a layout pattern for a target process technology, the method comprising:
obtaining an archetype layout providing a valid layout pattern for the cell based on design rules of the target process technology;
receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated;
performing a schematic sizing operation on the input data file, based on schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, to generate an output data file providing a process technology dependent schematic of the circuit component;
obtaining a process technology independent layout representation associated with the circuit component, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations;
performing a cell generation operation using the process technology independent layout representation in combination with the output data file and layout data determined from the archetype layout to generate the integrated circuit layout of the cell,
wherein the cell generation operation comprises:
analyzing the archetype layout to create a set of compaction nodes, each compaction node being associated with an edge of a feature in the archetype layout;
establishing connection lines between pairs of edges, and for each pair of edges allocating the associated connection lines to the compaction node for each edge in that pair;
allocating forces to each connection line; and
applying a solving algorithm to manipulate locations of the edges based on the forces; and

manufacturing the integrated circuit or causing the integrated circuit to be manufactured from or based on the integrated circuit layout of the cell.

2. The method as claimed in claim 1 , wherein said performing a schematic sizing operation comprises:
evaluating the source schematic based on specified requirements for the target process technology to determine schematic constraints on component elements of the cell used to implement the circuit component defined by the cell;
evaluating the archetype layout to determine any layout constraints on said component elements that are dictated by the integrated circuit layout of the cell; and
generating the process technology dependent schematic taking into account the schematic constraints and the layout constraints.

3. The method as claimed in claim 2 , wherein the component elements are configured in multiple hierarchical levels, and schematic constraints and layout constraints are associated with component elements at more than one hierarchical level.

4. The method as claimed in claim 2 , wherein at least some of said component elements are transistors, and the source constraints and layout constraints applied to the transistors identify size constraints on transistor features.

5. The method as claimed in claim 4 , wherein said size constraints comprises at least one of:
an indication of multiple transistors that need to have the same size;
an indication of a total size for multiple associated transistors; and
an indication of minimum and maximum sizes for one or more transistors.

6. The method as claimed in claim 1 , wherein the archetype layout is configured such that sizes of transistors defined by the archetype layout are maximized based on constraints dictated by the design rules.

7. The method as claimed in claim 1 , further comprising:
generating the technology independent layout representation with reference to the archetype layout.

8. The method as claimed in claim 7 , further comprising populating a first database of process technology independent layout representations by:
receiving an input archetype layout of a particular cell, providing a valid layout pattern for generating within the target process technology the circuit component defined by that particular cell;
superimposing said grid array on that input archetype layout;
identifying a plurality of regular-shaped sections forming the input archetype layout;
transforming those regular-shaped sections into segments snapped to the grid array to generate a process technology independent layout representation associated with the circuit component defined by the particular cell; and
storing the generated process technology independent layout representation in the first database.

9. The method as claimed in claim 8 , wherein the generated process technology independent layout representation stored in the first database is used as the process technology independent layout representation obtained when generating the integrated circuit layout of the cell whose defined circuit component is of a same type as the circuit component defined by the particular cell having the input archetype layout.

10. The method as claimed in claim 8 , wherein said transforming the regular-shaped sections into segments snapped to the grid array comprises:
for pairs of overlapping regular-shaped sections, snapping those pairs to the grid array such that a connection between the overlapping regular-shaped sections of each pair is located at a grid location of the grid array.

11. The method as claimed in claim 1 , wherein said analyzing the archetype layout comprises:
analyzing layout shapes in the archetype layout to break up the layout shapes into overlapping rectangles; and
creating compaction nodes for each edge of each overlapping rectangle, the method further comprising:
for the overlapping rectangles formed from each layout shape, determining which connection lines intersect by at least a specified amount, and associating forces with those connection lines such that those connection lines remain connected during the cell generation operation.

12. The method as claimed in claim 11 , wherein during said process of breaking up the layout shape into overlapping rectangles, any rectangle whose shorter dimension is less than a predetermined threshold is discarded.

13. The method as claimed in claim 1 , wherein the archetype layout obtained to provide a valid layout pattern for the cell based on design rules of the target process technology is generated by performing:
inputting an existing archetype layout for the cell conforming to a first cell architecture;
obtaining cell dimension data for a second cell architecture;
performing a layout resizing operation on the existing archetype layout to generate a new archetype layout conforming to the second cell architecture;
employing the new archetype layout as the obtained archetype layout.

14. The method as claimed in claim 1 , wherein obtaining the archetype layout providing the valid layout pattern comprises:
generating an indication of valid pin access layout patterns for the integrated circuit layout of the cell defining the circuit component, the integrated circuit layout defining layout patterns for a number of process layers, including an input/output (I/O) pin layout pattern for a first process layer, the I/O pin layout pattern defining a plurality of I/O pins;
providing in association with a second process layer a plurality of routing tracks extending through the cell, the routing tracks being used for provision of pin access connections defined by a pin access layout pattern;
detecting hit points for the cell, where each hit point identifies a segment of a routing track that overlaps one of said I/O pins;
determining a plurality of hit point combinations for the

Assignees

• Advanced Risc Mach Ltd

Inventors

• De Dood Paul
• Frederick Marlin Wayne
• Wang Jerry Chaoyuan
• Lee Brian Douglas Ngai
• Cline Brian Tracy
• Xu Xiaoqing
• Chen Andy Wangkun
• Chong Yew Keong
• Shore Tom
• Thyagarajan Sriram
• Yeung Gus
• Jiang Yanbin
• Pacaud Emmanuel Jean Marie Olivier
• Pauly Matthieu Domonique Henri
• Li Sylvia Xiuhui
• Achuthan Thanusree
• Albers Daniel J
• Granda David William

Classifications

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F17/5072

  Physics · mapped topic

• G06F17/5068 Primary

  Physics · mapped topic

• G06F17/5077

  Physics · mapped topic