Semiconductor process

Patent metadata

Field	Value
Publication number	US-2018339901-A1
Application number	US-201715644430-A
Country	US
Kind code	A1
Filing date	Jul 7, 2017
Priority date	May 25, 2017
Publication date	Nov 29, 2018
Grant date	—

Abstract

A semiconductor process including the following steps is provided. A wafer is provided. The wafer has a front side and a back side. The wafer has a semiconductor device on the front side. A protection layer is formed on the front side of the wafer. The protection layer covers the semiconductor device. A material of the protection layer includes a photoresist material. A surface hardening treatment process is performed on the protection layer. A first patterning process is performed on the back side of the wafer. The semiconductor process can effectively protect the front side of the wafer during a backside process.

First claim

What is claimed is:

1 . A semiconductor process, comprising:
providing a wafer, wherein the wafer has a front side and a back side, and the wafer has a semiconductor device on the front side; forming a protection layer on the front side of the wafer, wherein the protection layer covers the semiconductor device, and a material of the protection layer comprises a photoresist material; performing a surface hardening treatment process on the protection layer; and performing a first patterning process on the back side of the wafer.

2 . The semiconductor process according to claim 1 , wherein the semiconductor device comprises a microelectromechanical system (MEMS) device or a logic device.

3 . The semiconductor process according to claim 2 , wherein the MEMS device comprises a sensor device.

4 . The semiconductor process according to claim 3 , wherein the sensor device comprises an accelerometer, a MEMS microphone, a photosensor or a gas sensor.

5 . The semiconductor process according to claim 1 , further comprising, before or after forming the protection layer, performing a thinning process on the back side of the wafer.

6 . The semiconductor process according to claim 5 , wherein the thinning process comprises a grinding process.

7 . The semiconductor process according to claim 1 , wherein the photoresist material comprises an I-line photoresist, an ArF photoresist or a KrF photoresist.

8 . The semiconductor process according to claim 1 , further comprising, before performing the surface hardening treatment process, performing a second patterning process on the protection layer.

9 . The semiconductor process according to claim 8 , wherein the second patterning process comprises a lithography process.

10 . The semiconductor process according to claim 1 , wherein the surface hardening treatment process comprises performing an ion implantation process, an UV treatment or an e-beam treatment on the protection layer.

11 . The semiconductor process according to claim 10 , wherein a dopant of the ion implantation process comprises phosphorus, boron or arsenic.

12 . The semiconductor process according to claim 10 , wherein an implantation concentration of the ion implantation process is 1×10 15 ions/cm 2 to 4×10 15 ions/cm 2 .

13 . The semiconductor process according to claim 10 , wherein an implantation energy of the ion implantation process is 50 keV to 100 keV.

14 . The semiconductor process according to claim 10 , further comprising, before performing the ion implantation process, performing an anneal process on the protection layer.

15 . The semiconductor process according to claim 14 , wherein a temperature of the anneal process is 150° C. to 250° C.

16 . The semiconductor process according to claim 1 , wherein the first patterning process comprises:
forming a patterned photoresist layer on the back side of the wafer; and removing a portion of the wafer from the back side of the wafer using the patterned photoresist layer as a mask.

17 . The semiconductor process according to claim 16 , wherein a method for removing the portion of the wafer comprises a dry etching process, a wet etching process or a combination thereof.

18 . The semiconductor process according to claim 17 , wherein the dry etching process comprises a deep reactive ion etching (DRIE) process.

19 . The semiconductor process according to claim 16 , further comprising, after removing the portion of the wafer, removing the patterned photoresist layer.

20 . The semiconductor process according to claim 1 , further comprising, after performing the first patterning process, removing the protection layer.

Assignees

• United Microelectronics Corp

Inventors

• Wei Guo-Chih
• Chen Weng-Yi
• Li Shih-Wei

Classifications

• H10P76/2042

  using lasers · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P14/6542

  by using coherent radiation, e.g. using a laser · CPC title