CMOS and pressure sensor integrated on a chip and fabrication method

Patent metadata

Field	Value
Publication number	US-9790082-B1
Application number	US-201615271627-A
Country	US
Kind code	B1
Filing date	Sep 21, 2016
Priority date	Sep 21, 2016
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.

First claim

What is claimed is:

1. A device comprising:
a silicon-on-insulator (SOI) substrate, said SOI substrate having a first silicon layer, a second silicon layer, and an insulator layer interposed between said first and second silicon layers;
a structural layer formed on said first silicon layer of said SOI substrate, said structural layer having a first conductivity type;
a well region formed in said structural layer, said well region having a second conductivity type that is opposite from said first conductivity type;
at least one resistor in said well region;
a metallization structure formed over said well region and said at least one resistor;
a first cavity extending through said metallization structure overlying said well region; and
a second cavity extending through said second silicon layer of said SOI substrate, said second cavity stopping at one of said first silicon layer and said insulator layer, wherein said well region interposed between said first and second cavities defines a diaphragm of a pressure sensor.

2. The device of claim 1 further comprising a shield layer formed over said well region.

3. The device of claim 1 further comprising electrical contacts in said metallization structure, said electrical contacts being electrically connected to said at least one resistor in said well region, and said electrical contacts being laterally displaced away from said first cavity.

4. The device of claim 1 wherein said metallization structure includes multiple metallization layers, and said first cavity extends through all of said metallization layers.

5. The device of claim 1 further comprising a second substrate coupled to an outer surface of said second silicon layer, said second substrate sealing said second cavity from an environment external to said device.

6. The device of claim 1 further comprising a complementary metal oxide semiconductor (CMOS) integrated circuit on said first silicon layer of said SOI substrate, said CMOS integrated circuit being electrically isolated from said pressure sensor.

7. A method of fabricating a pressure sensor comprising:
forming a structural layer on a first silicon layer of a silicon-on-insulator (SOI) substrate, said SOI substrate having said first silicon layer, a second silicon layer, and an insulator layer interposed between said first and second silicon layers, and said structural layer having a first conductivity type;
forming a well region in said structural layer, said well region having a second conductivity type that is opposite from said first conductivity type;
forming at least one resistor in said well region;
forming a first cavity extending through said metallization structure overlying said well region; and
forming a second cavity extending through said second silicon layer of said SOI substrate, said second cavity stopping at one of said first silicon layer and said insulator layer, wherein said well region interposed between said first and second cavities defines a diaphragm of said pressure sensor.

8. The method of claim 7 wherein said metallization structure includes multiple metallization layers, and said first cavity extends through all of said metallization layers.

9. The method of claim 7 wherein said forming said second cavity comprises performing a deep reactive ion etch (DRIE) process to form said second cavity.

10. The method of claim 7 further comprising:
applying a protection coating in said first cavity and over an exterior surface of said metallization structure prior to said forming said second cavity; and
removing said protection coating following formation of said second cavity.

11. The method of claim 7 further comprising sealing said second cavity from an external environment.

12. The method of claim 11 wherein said sealing comprises coupling a second substrate to an outer surface of said second silicon layer following formation of said second cavity.

13. The method of claim 7 further comprising forming a complementary metal oxide semiconductor (CMOS) integrated circuit on said first silicon layer of said SOI substrate.

14. The method of claim 13 wherein said forming said CMOS integrated circuit on said first silicon layer is performed concurrent with said forming said well region and said forming said at least one resistor.

15. The method of claim 13 further comprising forming an isolation structure between said pressure sensor and said CMOS integrated circuit, said isolation structure electrically isolating said CMOS integrated circuit from said pressure sensor.

16. A device comprising:
a silicon-on-insulator (SOI) substrate, said SOI substrate having a first silicon layer, a second silicon layer, and an insulator layer interposed between said first and second silicon layers;
a structural layer formed on said first silicon layer of said SOI substrate, said structural layer having a first conductivity type;
a pressure sensor having a well region and at least one resistor formed in said structural layer;
a complementary metal oxide semiconductor (CMOS) integrated circuit on said first silicon layer of said SOI substrate in said structural layer; and
metallization structure formed over said well region, said at least one resistor, and said CMOS integrated circuit, wherein a first cavity extends through said metallization structure overlying said well region and a second cavity extends through said second silicon layer of said SOI substrate, said second cavity stopping at one of said first silicon layer and said insulator layer, and wherein said well region interposed between said first and second cavities defines a diaphragm of said pressure sensor.

17. The device of claim 16 further comprising an isolation structure between said diaphragm of said pressure sensor and said CMOS integrated circuit, said isolation structure electrically isolating said CMOS integrated circuit from said pressure sensor.

18. The device of claim 16 wherein said metallization structure includes electrical contacts, said electrical contacts being connected to said at least one resistor, and said electrical contacts being laterally displaced away from said first cavity.

19. The device of claim 16 wherein said metallization structure includes multiple metallization layers, and said first cavity extends through all of said metallization layers.

20. The device of claim 16 further comprising a second substrate coupled to an outer surface of said second silicon layer, said second substrate sealing said second cavity from an environment external to said device.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Liu Lianjun
• Bose Amitava

Classifications

• B81B2207/07

  Interconnects · CPC title

• B81B2201/0264

  Pressure sensors · CPC title

• B81B3/0027 Primary

  Structures for transforming mechanical energy, e.g. potential energy of a spring into translation, sound into translation · CPC title

• B81C2201/0132

  Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling · CPC title

• B81C1/00246

  Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate · CPC title