Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-2018240726-A1
Application number	US-201815961839-A
Country	US
Kind code	A1
Filing date	Apr 24, 2018
Priority date	Jun 8, 2014
Publication date	Aug 23, 2018
Grant date	—

Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die; and an encapsulant layer having an encapsulant material, wherein the encapsulant layer contacts and completely covers each of the first and second sidewalls of the die, wherein the encapsulant layer does not contact the first major surface of the die.

2 . The semiconductor package of claim 1 wherein the encapsulant layer is a first encapsulant layer, the semiconductor package comprising a second encapsulant layer disposed on and covering the first major surface of the die, wherein the first encapsulant layer extends downwardly beyond the second encapsulant layer to cover a bottommost planar surface of the second encapsulant layer.

3 . The semiconductor package of claim 1 wherein the encapsulant layer comprises a topmost planar surface which is coplanar to the second major surface of the die.

4 . The semiconductor package of claim 1 wherein the encapsulant layer does not contact the second major surface of the die.

5 . The semiconductor package of claim 1 wherein the encapsulant layer comprises a bottommost planar surface which is coplanar to the first major surface of the die.

6 . The semiconductor package of claim 1 wherein the encapsulant layer comprises an arc shape profile disposed adjacent to each of the first and second sidewalls, wherein the arc profile is positioned proximate to the first major surface of the die.

7 . The semiconductor package of claim 1 wherein the encapsulant layer extends upwardly beyond the second major surface of the die.

8 . The semiconductor package of claim 7 wherein the encapsulant layer completely covers the second major surface of the die, the encapsulant layer comprising a flowable polymeric material.

9 . The semiconductor package of claim 1 comprising a protective layer contacting and completely covering the second major surface of the die, wherein the protective layer comprises a material which is different from the encapsulant material.

10 . A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die; a protective layer, the protective layer comprising a resin film and an adhesive layer, wherein the protective layer is disposed on and completely covers the second major surface of the die, wherein the protective layer comprises a bottom major surface in direct contact to the second major surface of the die, and a top major surface positioned over the bottom major surface; and an encapsulant layer having an encapsulant material, wherein the encapsulant layer is disposed on and completely covers each of the first and second sidewalls of the die.

11 . The semiconductor package of claim 10 wherein the protective layer extends laterally beyond the first and second sidewalls of the die.

12 . The semiconductor package of claim 11 wherein a topmost planar surface of the encapsulant layer is coplanar with the second major surface of the die.

13 . The semiconductor package of claim 10 wherein the encapsulant layer does not contact the first major surface of the die.

14 . The semiconductor package of claim 13 wherein the encapsulant layer extends upwardly beyond the second major surface of the die, wherein a topmost planar surface of the encapsulant layer is coplanar with the top major surface of the protective layer.

15 . A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die; an encapsulant layer having an encapsulant material, wherein the encapsulant layer does not contact the first and second major surfaces of the die.

16 . The semiconductor package of claim 15 wherein the encapsulant layer contacts and completely covers each of the first and second sidewalls of the die.

17 . The semiconductor package of claim 16 comprising a protective layer contacting and completely covering the second major surface of the die, wherein the protective layer comprises a material which is different from the encapsulant material.

18 . The semiconductor package of claim 17 wherein the protective layer comprises a thermoplastic polymer based resin film and a thermosetting type of adhesive.

19 . The semiconductor package of claim 15 wherein the encapsulant layer comprises a bottommost planar surface which is coplanar to the first major surface of the die.

20 . The semiconductor package of claim 15 wherein the encapsulant layer is a second encapsulant layer disposed over a first encapsulant layer, wherein the first encapsulant layer contacts and covers the first major surface of the die, the second encapsulant layer extending over and covering a bottom planar surface of the first encapsulant layer, wherein the first and second encapsulant layers are separate and distinct layers.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Suthiwongsunthorn Nathapong
• Dimaano Antonio Jr Bambalan
• Huang Rui
• Tan Hua Hong
• Le Kriangsak Sae
• Ho Beng Yeung
• De Vera Nelson Agbisit
• Robles Roel Adeva
• Micla Wedanni Linsangan

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W46/301

  for alignment · CPC title