Leverage cycle stealing within optimization flows

Patent metadata

Field	Value
Publication number	US-2018239844-A1
Application number	US-201715817741-A
Country	US
Kind code	A1
Filing date	Nov 20, 2017
Priority date	Feb 23, 2017
Publication date	Aug 23, 2018
Grant date	—

Abstract

A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

First claim

What is claimed is:

1 . A computer program product for implementing timing adjustments in an integrated circuit, the computer program product comprising:
one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising: program instructions to calculate an input timing slack at an input to a latch by program instructions to subtract an input arrival time to the latch from an input required arrival time of the latch; program instructions to calculate an output timing slack at an output to the latch by program instructions to subtract an output arrival time of the latch from an output required arrival time from the latch; program instructions to perform cycle stealing to improve the output timing slack by program instructions to modify the required arrival time of the latch and the required output arrival time; program instructions to reduce the output timing slack by a pessimism amount; program instructions to perform optimization by program instructions to make design modifications in the integrated circuit to improve the input timing slack and the output timing slack until a desired slack goal is achieved; and program instructions to increase the output timing slack by the pessimism amount.

2 . The computer program product according to claim 1 , further comprising:
program instructions perform final power recovery.

3 . The computer program product according to claim 1 , wherein the latch comprises at least one of the following: an unbalanced input timing slack and output timing slack, the output timing slack above a target threshold, or a cycle boundary occurring earlier than an end of an active clock interval.

4 . The computer program product according to claim 1 , wherein program instructions to perform optimization comprises at least one of the following:
program instructions to modify a physical size of a logic device in the integrated circuit; program instructions to change a wire size in the integrated circuit; and program instructions to swap design equivalents.

5 . The computer program product according to claim 1 , wherein the desired slack goal comprises the output timing slack equal to zero.

6 . The computer program product according to claim 1 , wherein the desired slack goal comprises the input timing slack equal to the output timing slack.

7 . A computer system for implementing timing adjustments in an integrated circuit, the computer system comprising:
one or more computer processors, one or more computer-readable storage media, and program instructions stored on the one or more computer-readable storage media for execution by at least one of the one or more processors, the program instructions comprising: program instructions to calculate an input timing slack at an input to a latch by program instructions to subtract an input arrival time to the latch from an input required arrival time of the latch; program instructions to calculate an output timing slack at an output to the latch by program instructions to subtract an output arrival time of the latch from an output required arrival time from the latch; program instructions to perform cycle stealing to improve the input timing slack by program instructions to modify the input required arrival time of the latch and the output arrival time; program instructions to reduce the output timing slack by a pessimism amount; program instructions to perform optimization by program instructions to make design modifications in the integrated circuit to improve the input timing slack and the output timing slack until a desired slack goal is achieved; and program instructions to increase the output timing slack by the pessimism amount.

8 . The computer system according to claim 7 , further comprising:
program instructions perform final power recovery.

9 . The computer system according to claim 7 , wherein the latch comprises at least one of the following: an unbalanced input timing slack and output timing slack, the output timing slack above a target threshold, or a cycle boundary occurring earlier than an end of an active clock interval.

10 . The computer system according to claim 7 , wherein program instructions to perform optimization comprises at least one of the following:
program instructions to modify a physical size of a logic device in the integrated circuit; program instructions to change a wire size in the integrated circuit; and program instructions to swap design equivalents.

11 . The computer system according to claim 7 , wherein program instructions to perform final power recovery comprises:
program instructions to remove unnecessary output timing slack improvement; and program instructions to remove unnecessary input timing slack improvement.

12 . The computer system according to claim 7 , wherein the pessimism amount is based on at least one of the following:
the input timing slack; program instructions to estimate a maximum possible slack improvement; and program instructions to calculate a difference between a current cycle boundary time and a time which corresponds with an end of an active clock interval.

Assignees

• IBM

Inventors

• Hieter Nathaniel D
• Kalafala Kerim
• Suess Alexander J

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081

  Physics · mapped topic

• G06F17/505 Primary

  Physics · mapped topic