Leverage cycle stealing within optimization flows

Patent metadata

Field	Value
Publication number	US-10216875-B2
Application number	US-201715439991-A
Country	US
Kind code	B2
Filing date	Feb 23, 2017
Priority date	Feb 23, 2017
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

First claim

What is claimed is:

1. A method of implementing timing adjustments in an integrated circuit, the method comprising:
calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time of the latch;
calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch;
performing cycle stealing to improve the output timing slack by modifying the input required arrival time of the latch and the output arrival time;
reducing the output timing slack by a pessimism amount;
performing optimization by making design modifications in the integrated circuit to improve the input timing slack and the output timing slack until a desired slack goal is achieved;
increasing the output timing slack by the pessimism amount; and
generating a final integrated circuit based on the final power recovery and creating a semiconductor chip based on the final integrated circuit.

2. The method according to claim 1 , further comprising:
performing final power recovery.

3. The method according to claim 2 , wherein performing final power recovery comprises:
removing unnecessary output timing slack improvement; and
removing unnecessary input timing slack improvement.

4. The method according to claim 1 , wherein the latch comprises at least one of the following: an unbalanced input timing slack and output timing slack, the output timing slack above a target threshold, or a cycle boundary occurring earlier than an end of an active clock interval.

5. The method according to claim 1 , wherein performing optimization comprises at least one of the following:
modifying a physical size of a logic device in the integrated circuit;
changing a wire size in the integrated circuit; and
swapping design equivalents.

6. The method according to claim 1 , wherein the desired slack goal comprises the output timing slack equal to zero.

7. The method according to claim 1 , wherein the desired slack goal comprises the input timing slack equal to the output timing slack.

8. The method according to claim 1 , wherein the pessimism amount is based on at least one of the following:
the input timing slack;
estimating a maximum possible slack improvement; and
calculating a difference between a current cycle boundary time and a time which corresponds with an end of an active clock interval.

Assignees

• IBM

Inventors

• Hieter Nathaniel D
• Kalafala Kerim
• Suess Alexander J

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F17/5081

  Physics · mapped topic

• G06F17/505

  Physics · mapped topic