Fan-out circuit packaging with integrated lid

Patent metadata

Field	Value
Publication number	US-2018166356-A1
Application number	US-201615377496-A
Country	US
Kind code	A1
Filing date	Dec 13, 2016
Priority date	Dec 13, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

Various embodiments include integrated circuit (IC) package structures. In some cases, an IC package includes: a carrier having a recess; a plurality of IC chips coupled with the carrier inside the recess, the plurality of IC chips each including a plurality of connectors; a thermally conductive material between the plurality of IC chips and the carrier within the recess, the thermally conductive material coupling the plurality of IC chips with the carrier; a dielectric layer contacting the plurality of IC chips and the carrier; a redistribution layer (RDL) contacting the dielectric layer and the plurality of connectors, the RDL including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent IC chips in the plurality of IC chips; and a set of solder balls contacting the RDL and connected with the plurality of fan-out vias.

First claim

1 . An integrated circuit (IC) package comprising:
a carrier having a recess; a plurality of integrated circuit chips coupled with the carrier inside the recess, the plurality of integrated circuit chips each including a plurality of connectors; a thermally conductive material between the plurality of integrated circuit chips and the carrier within the recess, the thermally conductive material coupling the plurality of integrated circuit chips with the carrier; a dielectric layer contacting the plurality of integrated circuit chips and the carrier, wherein the dielectric layer is free of epoxy mold compound; a redistribution layer (RDL) contacting the dielectric layer and the plurality of connectors, the RDL including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent integrated circuit chips in the plurality of integrated circuit chips; and a set of solder balls contacting the RDL and connected with the plurality of fan-out vias.

2 . (canceled)

3 . (canceled)

4 . The IC package according to claim 1 , wherein the RDL includes at least one of polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), phenolic resin, olefin or an epoxy molding compound.

5 . The IC package according to claim 1 , wherein the at least one connector contacts a surface of each of the integrated circuit chips opposite the thermally conductive material.

6 . The IC package according to claim 1 , wherein the plurality of connectors include a set of copper pillars or vias.

7 . (canceled)

8 . The IC package according to claim 1 , wherein the dielectric layer has a thickness measured from an upper surface of the carrier, the dielectric layer thickness being approximately equal to a height of each of the plurality of connectors as measured from an upper surface of a corresponding one of the plurality of integrated circuit chips.

9 . (canceled)

10 . The IC package according to claim 1 , wherein the thermally conductive material includes solder or a thermally conductive gel.

11 . The IC package according to claim 1 , further comprising a ground contact contacting the carrier.

12 . An integrated circuit (IC) package comprising:
a carrier having a recess, wherein the carrier includes copper or aluminum and includes a base and sidewalls formed as a single piece of material; a plurality of integrated circuit chips coupled with the carrier inside the recess, the plurality of integrated circuit chips each including a plurality of connectors; a thermally conductive material between the plurality of integrated circuit chips and the carrier within the recess, the thermally conductive material coupling the plurality of integrated circuit chips with the carrier; a dielectric layer contacting the plurality of integrated circuit chips and the carrier, the dielectric layer having a thickness measured from an upper surface of the carrier, the dielectric layer thickness being approximately equal to a height of each of the plurality of connectors as measured from an upper surface of a corresponding one of the plurality of integrated circuit chips, wherein the dielectric layer is free of epoxy mold compound; a redistribution layer (RDL) contacting the dielectric layer and the plurality of connectors, the RDL including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent integrated circuit chips in the plurality of integrated circuit chips; and a set of solder balls contacting the RDL and connected with the fan-out vias.

13 . (canceled)

14 . The IC package according to claim 12 , wherein the RDL includes at least one of polyamide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), or an epoxy molding compound.

15 . The IC package according to claim 12 , wherein the at least one connector contacts a surface of each of the integrated circuit chips opposite the thermally conductive material.

16 . The IC package according to claim 12 , wherein the plurality of connectors include a set of copper pillars or copper vias.

17 . (canceled)

18 . (canceled)

19 . The IC package according to claim 12 , wherein the thermally conductive material includes solder or a thermally conductive gel.

20 . The IC package according to claim 1 , further comprising a ground contact contacting the carrier.

21 . The IC package of claim 1 , wherein the dielectric material fills any gaps between plurality of integrated circuit chips within the recess in the carrier.

22 . The IC package of claim 12 , wherein the dielectric material fills any gaps between plurality of integrated circuit chips within the recess in the carrier.

23 . The IC package of claim 1 , wherein the carrier includes a base and sidewalls formed as a single piece of material.

Assignees

• Globalfoundries Inc

Inventors

• Butt Shahid A
• Ramachandran Koushik
• Perfecto Eric D

Classifications

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/655

  Fan-out layouts · CPC title